cv_4th_big.jpgCMOS Circuit Design, Layout, and Simulation, Fourth Edition

John Wiley & Sons, July 2019. ISBN 9781119481515 (Errata)
 

 

 

 

 

 

 

 

 

 

Design, Layout, and Simulation Examples

Cadence Design System – ubiquitous commercial tools.

Electric VLSI Design System – free and powerful CAD system for chip design (schematics, layout, DRC, LVS, ERC, etc.).

LASI – the LAyout System for Individuals.

Mentor Graphics – IC design, verification, design-for-manufacturability, and test technologies.

Silvaco Analog/Mixed-Signal/RF EDA – easy-to-use tools with good process design kit (PDK) availability.

 

SPICE Software, MOSFET Models, and MOSIS Information

The book’s SPICE simulation examples are available at HSPICE, LTspice (author favorite!), PSpice, and WinSpice.

The 50 nm and 1 um MOSFET models are found in cmosedu_models.txt (see also, BSIM4 manual).

Information on generating a GDSII (stream) file and help on submitting chips to MOSIS can be found here.

 

Tutorials and Videos

Tutorials from CMOSedu.com: Bad design, Cadence, Electric VLSI, LTspice, and Silvaco EDA.

The first edition’s supporting material is found at the bottom of the webpage here.

Solutions.zip to the third edition's end-of-chapter problems and figures from the third edition and mixed-signal book.

 

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