Information for designers that fabricate through MOSIS from CMOSedu.com
MOSIS customers, and anyone with questions about MOSIS, are invited to try using the new MOSIS Customer Support and Inquiry System at support.mosis.com.
Information about the MOSIS Educational Program (MEP) is found here.
Below are examples of how to fill out the forms for submitting designs (in GDS format) for fabrication through MOSIS in ON’s C5 process (500 nm, 3 metal layers, 2 poly layers, see information from ON here)
To generate a GDS file
A GDS file of your chip may be generated in the Electric CAD system by going to File -> Export -> GDS II (Stream)…
A GDS file can be read into Electric using File -> Import -> GDS II (Stream)…
A GDS file can be generated in Cadence IC61 via the CIW and File -> Export -> Stream (image)
Next, in some cases (the beta version of the NCSU Cadence IC61 setups, but not the IC51 setups), you need to save a layer map corresponding to the MOSIS GDS layers into the appropriate technology library directory (NCSU_TechLib_ami06)
An example for the C5 process is NCSU_TechLib_ami06.layermap (can only be saved, not viewed) or, as a text file so it’s viewable, here
Save (overwrite) the layer map file above (right click) into $HOME/ncsu-cdk-1.6.0.beta/lib/NCSU_TechLib_ami06
Finally, if the cell you want to fabricate is called CHIP and it’s in a library called PxC_CHIP, then here is how the Stream Out menu is setup (hit Translate to generate the stream, aka GDS, file)
The stream (GDS) file is saved in your working directory
Here is an example of how to generate a GDS file using IC51 (start, as above, in the CIW and File -> Export -> Stream).
Note that the period in the Run Directory field indicates that the GDS file will be placed in the directory where you started Cadence.
To check that you have generated the GDS file correctly using Cadence IC51, IC61, Electric, or whatever layout tool you are using, download the OwlVision GDSII Viewer (double click on the OwlVision.jar file to run the program) and compare the layers seen using this tool to the layers you are using.
To submit a design to
MOSIS
1) To begin a chip fabrication start by requesting a new project using https://www.mosis.com/Webforms/new_project_scmos.html (below). Note that since the chip fabricated in this example is used to test structures for implementing avalanche photodetectors (APDs) Fill was not authorized (since the metal fill may block the light from hitting the APD). Other concerns are that the silicide (not used in C5) or automatic fill (found in other processes) may block the light from hitting the APD. There are layout layers that can be used to ensure that the APD isn’t covered (such as the silicide and fill block layers). In general, it’s okay to specify “Yes” to the “Fill Authorized:” question to help your chip meet the minimum density requirements for CMP. See additional comments here.
2) The MOSIS Educational Program (MEP) instructional account, provides 5 chips per submitted design in ON’s C5 or IBM’s 7RF processes (see: http://www.mosis.com/Faqs/faq-education.html). All to none of the 5 chips can be packaged in a 40-pin DIP. If 2 of your designs are to be packaged then 3 should be specified in the unpackaged (bare die) field as seen below.
3) Next fill out the Fabricate Form, https://www.mosis.com/Webforms/fabricate.html (see below).
4) Download the mosis crc executable for determining the Checksum and Count here. In Windows Start -> Run -> Cmd to open a terminal then navigate to where you saved this executable and the binary GDS file: mosiscrc -b APD_Test_Chip.gds
5) To determine the IP address of the computer you are using (FTP Send Host), which must also be the computer used to FTP your design to MOSIS, go to, ipmonkey.com or, more reliably since some computer networks use different IP addresses for web browsing and FTPing, use gmail.
a) FTP your GDS to ftp.design.mosis.com (an example using Windows Explorer is seen here)
b) The FTP username is your Design Number and the password is the FTP Send Password you specify below.
6) You will receive emails, at the address specified above (presumably at your email address, not mine ;-), after you have submitted these forms and after you have successfully FTPed your GDS file to MOSIS.
Some other notes.
- Do not submit chips with pixilated text or graphics that fail the DRCs. Below is an example (used as a label on a chip near a bonding pad).
- An example of a layout where pixilated text may be okay, because the chip was fabricated in an older CMOS process, is seen below.
- In a smaller IC process (e.g., < 500 nm CMOS) a problem with pixilated text/graphics has to do with chemical-mechanical planarization (CMP) and clean patterning.
- Crud from the smaller dimensions of the patterned materials can be generated that interferes with the CMP process.
- So unless you are designing in an older process the chip you submit should pass DRCs (no pictures!)
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