Homework assignments for ECE 510/410 Spring 2008

Homework guidelines are found here.

All layouts and schematics should be drawn using Electric.

Simulations should be performed using LTspice.

Drawing schematics using LTspice will result in zero credit.

Course projects – Due Wednesday, May 7. Read the policy on the course webpage concerning turning in late work. These projects are NOT group efforts. What you turn in should be your own work. I will ask my TAs for help in looking for layouts that are common in two project jelib files (so do your own work!)

Your project reports should detail:

· The reasons for the topology you selected

· Design considerations

· Hand calculations with comparisons to simulations (with and without parasitics)

· A pin diagram for the layout (how to connect the layout to bond pads if we fabricate the design)

· Clear layout documentation (zoomed in and outlines of the layout for easy grading).

· Layout should be as “tight” as possible.

· Email me your (clean) Jelib file and project report in PDF or Word formats.

· I should be able to figure out what to simulate and how to simulate it without any effort (make sure this is very clear!) 

· I will have the MOSFET models in C:\Electric\C5_models.txt

· I’ll perform an LVS and a DRC on what you send (so make sure everything is clean before emailing me!)

· I should receive the electronic report and jelib via email (jbaker at boisestate.edu) prior to the beginning of class (5 pm) on Wednesday May 7, 2008.

EE 510/410 project –

1. In ECE5410_proj.jelib is a bandgap reference schematic. A bandgap is a common circuit used for generating a voltage reference of 1.25 V that doesn’t change [much] with temperature and VDD variations. The first part of the project, for both ECE 510 and 410, is to layout this bandgap. Note that I’ve already laid out the parasitic pnp device used as for the diode. Make sure you simulate the operation of the bandgap and can show the minimum VDD that the bandgap can have while still maintaining a 1.25 V output voltage (say to within +/- 25 mV or so). Note that the icon for the bandgap reference has 3 pins: VDD, GND, VREF. Also note that VREF can’t supply current (it can only be connected to the gates of MOSFETs).
2. The second part of the project for both ECE 510 and 410 is to design a circuit that senses an input voltage (you should use the bandgap from part 1 in this circuit). The output of the circuit is a logic 1, VDD, when the input is less than 15 V and a logic 0 (ground) when the input is greater than 15 V. The circuit’s input should draw no more than 10 uA of current and no less than 1 uA of current. The sensing circuit you design should have a built in hysteresis of at least 200 mV (but less than 500 mV). What this means, for 200 mV hysteresis, is that the output of circuit may go high when the input drops to 14.9 V and then low when the input goes beyond 15.1. This is the same thing found in a thermostat controlling your home’s heater. If you have your thermostat set at 70 degrees your heater may kick on when the temperature drops to 69 and then shut off when the house heats up to 71. This keeps the heater from cycling on and off. Characterize your design for VDD ranging from 4 to 5 V and for temperatures ranging from 0 to 100C. Note that your simulations use an icon of your total circuit (what you’ve designed and the bandgap reference) having 4 pins: VDD, GND, Vin, and Enable out.
3. For ECE 510 only use your design from part 2 to enable a ring oscillator that drives buffers that drive a charge pump that supplies 15 V +/- 250 mV with load currents ranging from 0 to 100 uA (the output of the charge pump is the input in part 2). Again characterize your design for VDD ranging from 4 to 5 V and for temperatures ranging from 0 to 100C. The final cell that I simulate should have VDD and ground inputs with a 15 V output voltage (in other words your final design with everything should be an icon with 3 pins, VDD, GND, and the 15V output). Note that in SPICE you can model the load current with a current pulse. Show how robust your design is for varying load currents (say a pulse from 0 to 100 uA or from 100 uA to 0 etc.) Some thought is required to demonstrate, via simulations, a robust design. I would also like you discuss the efficiency of the design. Ideally all of the power supplied by VDD, VDD*IVDD, is equal to the power delivered to the load, VLOAD*ILOAD. In a real circuit this won’t be the case since your circuit will dissipate power.

HW18 – due Wednesday, April 30, Problems: A12.1, A12.3, A13.1, and A13.2

HW17 – due Wednesday, April 16, Problems: A11.8, also send me the layout of your bandgap reference before 5 pm on this day per the way we’ve done this in the past (see below, that is, clean jelib, unique name, etc.)

HW16 – due Wednesday, April 9, Problems: A10.7, A10.8, A11.1, A11,2, A11.3

HW15 – due Wednesday, April 2, Problems: A10.1, A10.2, and A10.3. Do the optional SPICE simulations. Make sure you use Electric to draw the schematics.

HW14 – due Monday, March 31, repeat the first part of HW9 for an 11-stage ring oscillator with an enable (see Fig. 18.41 without the extra capacitors). The file you email me should have three icon views (the inverter, the NAND gate, and the ring oscillator), three layouts, and three schematics (of course the ring oscillator schematic uses the inverter and NAND icons), A6.13, A6.15, A6.16, A6.19.

HW13 – due Wednesday, March 19, repeat the first part of HW9 for a NOR gate, A6.6, A6.8, and A6.9.

HW12 – due Monday, March 17, repeat the first part of HW9 for a NAND gate (instead of an inverter). Please make sure your icon looks like a NAND gate (no box around the gate, solid fill, or other non-standard artwork), A6.2 and A6.4

HW11 – due Wednesday, March 5, A5.4, A5.7, A5.8, and A5.10

HW10 – due Monday, March 3, lay out a 100/2 and a 5/100 PMOS device (in as square of an area as possible). Show how to connect the devices to 4 pads (D, G, S, and VDD). Make sure you LVS and DRC your cells. A5.1, A5.2, and A5.3

HW9 – due Wednesday, February 27, lay out an inverter using a 20/2 PMOS and a 10/2 NMOS, make an icon for the inverter. Make sure you LVS and DRC your final cells (schematic, layout, icon). Email a clean (nothing in the library except for what’s required in this problem) jelib file with a name “myname.jelib” where myname is your name (of course) to jbaker at boisestate.edu before class starts on Wednesday (no simulations required at this point). Ensure you have set, in the Preferences, Tools, Well-Check, that your p-well (substrate for us since we are not using a twin-well process) must be connected to ground and the n-well must be connected to VDD. Of course, turn in hardcopy (say two pages) showing the solution to this problem for the graders.

HW8 – due Monday, February 25, A4.1, A4.2, A4.3

HW7 – due Wednesday, February 20, A3.3, A3.4, A3.5, A3.11, and A3.12

HW6 – due Wednesday, February 13, 1) Lay out a padframe for a chip size of 1.5 mm square assuming that the pads are made with metal3 (only) and are 75 um square. What is the parasitic capacitance of the bonding pad? Ensure that you are using the C5 process scale factor (300 nm) and parasitics. 2) repeat part 1) but use pads that are made with metals 1, 2, and 3 (noting that the metal layers are connected together so that any metal layer can be run into the pad). Again what is the parasitic capacitance of the pad? 3) problems A3.1, A3.2

HW5 – due Monday, February 11, 1) Layout a diode using n-well and p-substrate that has an area (of n-well) of 12 by 12. DRC and LVS your layout/schematic. 2) using this diode and the SPICE parameters seen in Ex. 2.4 simulate the DC behavior of the diode (IV curve), the diode’s reverse recovery time, and how you would measure the diode’s junction capacitance for a particular reverse bias potential between the n-well and substrate (in this class the substrate is grounded unless otherwise indicated). 3) problems A2.5, A2.7, and A2.8.

HW4 – due Wednesday, February 6, 1) generate an icon in Electric for the schematic of the design in HW3 (icons are only used in schematics, that is, they are not used in layouts). Show how the two circuit outputs change for a .DC sweep of VDD from 0 to 5V, A2.2, A2.3

HW3 – due Monday, February 4,

1) Design, lay out (using only the n-well layer), and simulate a circuit that provides two reference voltage outputs: 0.4VDD and 0.6VDD. The circuit’s inputs are VDD and GND. For your design use only the 10k resistor layout (as many times as needed) from HW2. Make sure you LVS and DRC your final design. Email a clean (nothing in the library except for what’s required in this problem) jelib file with a name “myname.jelib” where myname is your name (of course) to jbaker at boisestate.edu before class starts on Monday (I should be able to simulate your cells). Of course, turn in hardcopy showing the solution to this problem for the graders. The jelib you send to me is for me to ensure that you have a fundamental understanding of Electric, LTspice, and the thus the flow and likely won’t be graded (but the graders will grade your hardcopy solution!).

2) If a 100 ohm resistor is added from Vout to ground in the circuit seen in Fig. 1.24 then use hand calculations to determine the circuit’s behavior. Verify your hand calculations with SPICE (generate the netlist using Electric). Comment intuitively on why the effective RC time constant drops.

3) Simulate, using both an AC and a transient, or pulse input, simulation the circuit seen in Fig. 10.24b (a scope probe). Using hand calculations adjust the value of the variable 15 pF capacitor in the tip of the probe to ensure that there is a 1/10 divider between the probe’s tip and the input of the scope (note that some scope probes put the variable capacitor across the input of the scope and used a fix value, say 12 pF, in the probe’s tip). Verify with SPICE. Also plot the AC impedance at the probes tip against frequency (apply an AC test voltage to the probe tip then divide this voltage by the current flowing through it). At very low frequencies the resistance is 10 MEG while at high frequencies the impedance becomes capacitive. Note that this SPICE simulation should only have 6 components (an input voltage source, two resistor’s, and 3 capacitors). Further note that the resulting circuit should only have two signal nodes (the probe tip and the scope’s input).

HW2 – due Wednesday, January 30, 1) Layout a resistive divider using two nominally 10k, n-well resistors, do an LVS (NCC) on your cells (we will do this problem in class on 1/28 after we introduce the n-well layer), 2) sketch the time-domain input and output for the RC lowpass filter seen in Fig. 1.21 with R = 1k, C=1pF, and an input sinewave at frequency of 200e6 Hz having a peak amplitude of 1V. Verify your hand sketches with SPICE. 3) A1.7

HW1 – due Monday, January 28, Draw a box that measures 10 by 20 using the n-well layer, A1.3, A1.4, A1.5

Return