# header information:
Hece5410_s09|8.10

# Views:
Vicon|ic
Vlayout|lay
Vschematic|sch

# External Libraries:

Lspiceparts|spiceparts

# Technologies:
Tmocmos|ScaleFORmocmos()D300.0|mocmosAnalog()BT|mocmosNumberOfMetalLayers()I3

# Cell 1k_poly;1{lay}
C1k_poly;1{lay}||mocmos|1233085117191|1236107627095||DRC_last_good_drc_area_date()G1235072379376|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1235072379376
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-Polysilicon-1-Con|contact@0||100|0||||
NMetal-1-Polysilicon-1-Con|contact@1||0|0||||
Ngeneric:Invisible-Pin|pin@2||50|0|||||SIM_spice_card(D5G4;)SR1 L R 1k
NSilicide-Block-Node|plnode@0||49.5|0|90|4||
APolysilicon-1|net@7|||S0|contact@0||100|0|contact@1||0|0
EL||D5G2;|contact@1||U
ER||D5G2;|contact@0||U
X

# Cell 1k_poly;1{sch}
C1k_poly;1{sch}||schematic|1233085550095|1235071944457|
Ngeneric:Facet-Center|art@0||0|0||||AV
Nartwork:Opened-Polygon|art@1||6|0|12|4|||trace()V[-6/0,-4/0,-3/2,-2/-2,0/2,2/-2,3/0,6/0]
NWire_Pin|pin@0||0|0||||
NWire_Pin|pin@1||12|0||||
Ngeneric:Invisible-Pin|pin@2||6|4|||||SIM_spice_card(D5G2;)SR1 L R 1k
EL||D5G2;|pin@0||U
ER||D5G2;|pin@1||U
X

# Cell 10k;1{lay}
C10k;1{lay}||mocmos|1233085117191|1235070961157||DRC_last_good_drc_area_date()G1235070820397|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1235070820397
Ngeneric:Facet-Center|art@0||0|0||||AV
Ngeneric:Invisible-Pin|pin@2||0.5|0|||||SIM_spice_card(D5G4;)SR1 L R 10k
NMetal-1-Pin|pin@3||72.5|0||||
NN-Well-Node|plnode@0||0|0|156|12||A
NMetal-1-N-Well-Con|substr@0||-72|0||||
NMetal-1-N-Well-Con|substr@1||72.5|0.5||||
AMetal-1|net@1|||S2700|pin@3||72.5|0|substr@1||72.5|0.5
EL||D5G2;|substr@1||U
ER||D5G2;|substr@0||U
X

# Cell 10k;1{sch}
C10k;1{sch}||schematic|1233085550095|1233086730119|
Ngeneric:Facet-Center|art@0||0|0||||AV
Nartwork:Opened-Polygon|art@1||6|0|12|4|||trace()V[-6/0,-4/0,-3/2,-2/-2,0/2,2/-2,3/0,6/0]
NWire_Pin|pin@0||0|0||||
NWire_Pin|pin@1||12|0||||
Ngeneric:Invisible-Pin|pin@2||6|4|||||SIM_spice_card(D5G2;)SR1 L R 10k
EL||D5G2;|pin@0||U
ER||D5G2;|pin@1||U
X

# Cell Amp_gain_minus_one;1{ic}
CAmp_gain_minus_one;1{ic}||artwork|1232654851265|1232655276150|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Thicker-Polygon|art@1||0|0|6|10|||SCHEM_function(D5G1;Y2;)SAmp_gain_minus_one|trace()V[-3/-5,-3/5,3/5,3/-5,-3/-5]
Nschematic:Bus_Pin|pin@0||-5|0||||
Nschematic:Wire_Pin|pin@1||-3|0||||
Nschematic:Bus_Pin|pin@2||5|0|||RR|
Nschematic:Wire_Pin|pin@3||3|0|||RR|
Nschematic:Bus_Pin|pin@4||0|-8||||
Nschematic:Wire_Pin|pin@5||0|-5||||
Aschematic:wire|net@0|||0|pin@1||-3|0|pin@0||-5|0
Aschematic:wire|net@1|||1800|pin@3||3|0|pin@2||5|0
Aschematic:wire|net@2|||900|pin@5||0|-5|pin@4||0|-8
EIn||D5G2;|pin@0||U
EOut||D5G2;|pin@2||U
Egnd||D5G2;|pin@4||U
X

# Cell Amp_gain_minus_one;2{sch}
CAmp_gain_minus_one;2{sch}||schematic|1232653886697|1232655296176|
IAmp_gain_minus_one;1{ic}|Amp_gain@0||44|18|||D5G4;
IIdeal_op_amp;1{ic}|Ideal_op@1||24|4|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||2|6||||
NOff-Page|conn@1||37|4||||
NOff-Page|conn@2||13|-4||||
NWire_Pin|pin@2||19|6.25||||
NWire_Pin|pin@3||19|12||||
NWire_Pin|pin@4||32|12||||
NWire_Pin|pin@5||32|4||||
NWire_Pin|pin@6||5|6.25||||
NWire_Pin|pin@8||5|6||||
NWire_Pin|pin@9||15|2.5||||
NResistor|res@0||11|6.25|||||SCHEM_resistance(D5G1;Y1;)S1k
NResistor|res@1||23|12|||||SCHEM_resistance(D5G1;Y1;)S1k
Awire|net@3|||1800|res@0|b|13|6.25|pin@2||19|6.25
Awire|net@4|||900|pin@2||19|6.25|Ideal_op@1|Vinm|19|5.75
Awire|net@5|||0|res@1|a|21|12|pin@3||19|12
Awire|net@6|||900|pin@3||19|12|pin@2||19|6.25
Awire|net@7|||1800|res@1|b|25|12|pin@4||32|12
Awire|net@8|||900|pin@4||32|12|pin@5||32|4
Awire|net@13|||1800|conn@0|y|4|6|pin@8||5|6
Awire|net@14|||2700|pin@8||5|6|pin@6||5|6.25
Awire|net@15|||0|conn@1|a|35|4|pin@5||32|4
Awire|net@16|||0|res@0|a|9|6.25|pin@6||5|6.25
Awire|net@17|||0|pin@5||32|4|Ideal_op@1|Out|29|4
Awire|net@18|||2700|conn@2|y|15|-4|pin@9||15|2.5
Awire|net@20|||0|Ideal_op@1|Vinp|19|2.5|pin@9||15|2.5
EIn||D5G2;|conn@0|a|U
EOut||D5G2;|conn@1|y|U
Egnd||D5G2;|conn@2|a|U
X

# Cell Amp_gain_minus_ten;1{ic}
CAmp_gain_minus_ten;1{ic}||artwork|1232654851265|1232655276150|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Thicker-Polygon|art@1||0|0|6|10|||SCHEM_function(D5G1;Y2;)SAmp_gain_minus_ten|trace()V[-3/-5,-3/5,3/5,3/-5,-3/-5]
Nschematic:Bus_Pin|pin@0||-5|0||||
Nschematic:Wire_Pin|pin@1||-3|0||||
Nschematic:Bus_Pin|pin@2||5|0|||RR|
Nschematic:Wire_Pin|pin@3||3|0|||RR|
Nschematic:Bus_Pin|pin@4||0|-8||||
Nschematic:Wire_Pin|pin@5||0|-5||||
Aschematic:wire|net@0|||0|pin@1||-3|0|pin@0||-5|0
Aschematic:wire|net@1|||1800|pin@3||3|0|pin@2||5|0
Aschematic:wire|net@2|||900|pin@5||0|-5|pin@4||0|-8
EIn||D5G2;|pin@0||U
EOut||D5G2;|pin@2||U
Egnd||D5G2;|pin@4||U
X

# Cell Amp_gain_minus_ten;1{sch}
CAmp_gain_minus_ten;1{sch}||schematic|1232653886697|1232655365807|
IAmp_gain_minus_ten;1{ic}|Amp_gain@1||44|18|||D5G4;
IIdeal_op_amp;1{ic}|Ideal_op@1||24|4|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||2|6||||
NOff-Page|conn@1||37|4||||
NOff-Page|conn@2||13|-4||||
NWire_Pin|pin@2||19|6.25||||
NWire_Pin|pin@3||19|12||||
NWire_Pin|pin@4||32|12||||
NWire_Pin|pin@5||32|4||||
NWire_Pin|pin@6||5|6.25||||
NWire_Pin|pin@8||5|6||||
NWire_Pin|pin@9||15|2.5||||
NResistor|res@0||11|6.25|||||SCHEM_resistance(D5G1;Y1;)S1k
NResistor|res@1||23|12|||||SCHEM_resistance(D5G1;Y1;)S1k
Awire|net@3|||1800|res@0|b|13|6.25|pin@2||19|6.25
Awire|net@4|||900|pin@2||19|6.25|Ideal_op@1|Vinm|19|5.75
Awire|net@5|||0|res@1|a|21|12|pin@3||19|12
Awire|net@6|||900|pin@3||19|12|pin@2||19|6.25
Awire|net@7|||1800|res@1|b|25|12|pin@4||32|12
Awire|net@8|||900|pin@4||32|12|pin@5||32|4
Awire|net@13|||1800|conn@0|y|4|6|pin@8||5|6
Awire|net@14|||2700|pin@8||5|6|pin@6||5|6.25
Awire|net@15|||0|conn@1|a|35|4|pin@5||32|4
Awire|net@16|||0|res@0|a|9|6.25|pin@6||5|6.25
Awire|net@17|||0|pin@5||32|4|Ideal_op@1|Out|29|4
Awire|net@18|||2700|conn@2|y|15|-4|pin@9||15|2.5
Awire|net@20|||0|Ideal_op@1|Vinp|19|2.5|pin@9||15|2.5
EIn||D5G2;|conn@0|a|U
EOut||D5G2;|conn@1|y|U
Egnd||D5G2;|conn@2|a|U
X

# Cell Ex_1;1{sch}
CEx_1;1{sch}||schematic|1238524753678|1238707650503|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||17|1|||||SCHEM_capacitance(D5G1;)S10f
NGround|gnd@0||17|-3|-2|-2||
NTransistor|nmos@0||12|5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NWire_Pin|pin@0||12|10.5|||RRR|
Ngeneric:Invisible-Pin|pin@2||24|7|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vin Vin 0 DC 0 PULSE 0 5 0 1p 1p 500p 1n,.tran 1p 3n]
NWire_Pin|pin@4||6|3||||
Awire|VDD|D5G1;||2700|nmos@0|g|12|6|pin@0||12|10.5
Awire|Vin|D5G1;||0|nmos@0|s|10|3|pin@4||6|3
Awire|Vout|D5G1;||0|cap@0|a|17|3|nmos@0|d|14|3
Awire|net@1|||900|cap@0|b|17|-1|gnd@0||17|-2
X

# Cell Ex_2;1{sch}
CEx_2;1{sch}||schematic|1238524753678|1238708124012|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||17|1|||||SCHEM_capacitance(D5G1;)S10f
NGround|gnd@0||17|-3|-2|-2||
NGround|gnd@1||8|7|-2|-2||
Ngeneric:Invisible-Pin|pin@2||24|7|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vgnd gnd 0 DC 0,Vin Vin 0 DC 0 PULSE 0 5 0 1p 1p 500p 1n,.tran 1p 3n]
NWire_Pin|pin@6||6|3||||
NWire_Pin|pin@7||8|9||||
NWire_Pin|pin@8||10.5|9||||
NTransistor|pmos@0||10.5|5||||2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||25.5|1||||
Awire|Vin|D5G1;||0|pmos@0|s|8.5|3|pin@6||6|3
Awire|Vout|D5G1;||1800|pmos@0|d|12.5|3|cap@0|a|17|3
Awire|net@1|||900|cap@0|b|17|-1|gnd@0||17|-2
Awire|net@6|||2700|gnd@1||8|8|pin@7||8|9
Awire|net@7|||1800|pin@7||8|9|pin@8||10.5|9
Awire|net@8|||900|pin@8||10.5|9|pmos@0|g|10.5|6
X

# Cell Ex_3;1{sch}
CEx_3;1{sch}||schematic|1238524753678|1238708187118|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||17|1|||||SCHEM_capacitance(D5G1;)S10f
NGround|gnd@0||17|-3|-2|-2||
NGround|gnd@1||8|7|-2|-2||
NTransistor|nmos@0||10.5|-1|||RR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Invisible-Pin|pin@2||24|7|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vgnd gnd 0 DC 0,Vin Vin 0 DC 0 PULSE 0 5 0 1p 1p 500p 1n,.tran 1p 3n]
NWire_Pin|pin@6||6|3||||
NWire_Pin|pin@7||8|9||||
NWire_Pin|pin@8||10.5|9||||
NWire_Pin|pin@9||13.5|1||||
NWire_Pin|pin@10||13.5|3||||
NWire_Pin|pin@11||8|1.5||||
NWire_Pin|pin@12||8|3||||
NTransistor|pmos@0||10.5|5||||2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||10.5|-4||||
Awire|Vin|D5G1;||0|pin@12||8|3|pin@6||6|3
Awire|Vout|D5G1;||1800|pin@10||13.5|3|cap@0|a|17|3
Awire|net@1|||900|cap@0|b|17|-1|gnd@0||17|-2
Awire|net@6|||2700|gnd@1||8|8|pin@7||8|9
Awire|net@7|||1800|pin@7||8|9|pin@8||10.5|9
Awire|net@8|||900|pin@8||10.5|9|pmos@0|g|10.5|6
Awire|net@9|||1800|nmos@0|s|12.5|1|pin@9||13.5|1
Awire|net@10|||1800|pmos@0|d|12.5|3|pin@10||13.5|3
Awire|net@11|||2700|pin@9||13.5|1|pin@10||13.5|3
Awire|net@12|||3150|nmos@0|d|8.5|1|pin@11||8|1.5
Awire|net@13|||0|pmos@0|s|8.5|3|pin@12||8|3
Awire|net@14|||2700|pin@11||8|1.5|pin@12||8|3
Awire|net@15|||2700|pwr@0||10.5|-4|nmos@0|g|10.5|-2
X

# Cell Ex_4;1{sch}
CEx_4;1{sch}||schematic|1238524753678|1238708853859|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||17|1|||||SCHEM_capacitance(D5G1;)S10f
NGround|gnd@0||17|-3|-2|-2||
NTransistor|nmos@0||12|5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@1||7.5|5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@2||3|5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@3||-1.5|5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@4||-6.5|5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@5||-11|5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@6||-15.5|5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@7||-20|5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Invisible-Pin|pin@2||-4.5|-1|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vin Vin 0 DC 0 PULSE 0 5 0 1p 1p 5n 10n,.tran 10p 30n]
NWire_Pin|pin@6||-23.5|3||||
NWire_Pin|pin@7||-4|6||||
NPower|pwr@0||-4|9||||
Awire|Vin|D5G1;||0|nmos@7|s|-22|3|pin@6||-23.5|3
Awire|Vout|D5G1;||0|cap@0|a|17|3|nmos@0|d|14|3
Awire|net@1|||900|cap@0|b|17|-1|gnd@0||17|-2
Awire|net@2|||1800|nmos@1|d|9.5|3|nmos@0|s|10|3
Awire|net@4|||1800|nmos@3|d|0.5|3|nmos@2|s|1|3
Awire|net@5|||1800|nmos@5|d|-9|3|nmos@4|s|-8.5|3
Awire|net@6|||1800|nmos@7|d|-18|3|nmos@6|s|-17.5|3
Awire|net@7|||1800|nmos@4|d|-4.5|3|nmos@3|s|-3.5|3
Awire|net@9|||0|nmos@6|g|-15.5|6|nmos@7|g|-20|6
Awire|net@10|||1800|nmos@6|g|-15.5|6|nmos@5|g|-11|6
Awire|net@11|||1800|nmos@5|g|-11|6|nmos@4|g|-6.5|6
Awire|net@12|||1800|pin@7||-4|6|nmos@3|g|-1.5|6
Awire|net@13|||1800|nmos@3|g|-1.5|6|nmos@2|g|3|6
Awire|net@14|||1800|nmos@2|g|3|6|nmos@1|g|7.5|6
Awire|net@15|||1800|nmos@1|g|7.5|6|nmos@0|g|12|6
Awire|net@16|||1800|nmos@4|g|-6.5|6|pin@7||-4|6
Awire|net@17|||900|pwr@0||-4|9|pin@7||-4|6
Awire|net@18|||0|nmos@1|s|5.5|3|nmos@2|d|5|3
Awire|net@19|||0|nmos@5|s|-13|3|nmos@6|d|-13.5|3
X

# Cell Ex_5;1{sch}
CEx_5;1{sch}||schematic|1238524753678|1238709110719|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||6.5|-11.5|||||SCHEM_capacitance(D5G1;)S10f
NGround|gnd@0||6.5|-15.5|-2|-2||
NGround|gnd@1||-30.5|-16|-2|-2||
NGround|gnd@2||-26|-16|-2|-2||
NGround|gnd@3||-21.5|-16|-2|-2||
NGround|gnd@4||-17|-16|-2|-2||
NGround|gnd@5||-12|-16|-2|-2||
NGround|gnd@6||-7.5|-16|-2|-2||
NGround|gnd@7||-3|-16|-2|-2||
NGround|gnd@8||1.5|-16|-2|-2||
NTransistor|nmos@0||1.5|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@1||-3|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@2||-7.5|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@3||-12|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@4||-17|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@5||-21.5|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@6||-26|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@7||-30.5|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Invisible-Pin|pin@2||-26.5|-2|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vin Vin 0 DC 0 PULSE 0 5 0 1p 1p 5n 10n,.tran 10p 30n]
NWire_Pin|pin@6||-34|-9.5||||
NWire_Pin|pin@7||-14.5|-6.5||||
NWire_Pin|pin@8||4|-11.5||||
NWire_Pin|pin@9||4|-9.5||||
NWire_Pin|pin@10||-33|-11.5||||
NWire_Pin|pin@11||-33|-9.5||||
NWire_Pin|pin@13||-19|-11.5||||
NWire_Pin|pin@14||-14.5|-9.5||||
NWire_Pin|pin@15||-14.5|-11.5||||
NTransistor|pmos@0||-30.5|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@1||-26|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@2||-21.5|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@3||-17|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@4||-12|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@5||-7.5|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@6||-3|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@7||1.5|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||-14.5|-3.5||||
Awire|Vin|D5G1;||0|pin@11||-33|-9.5|pin@6||-34|-9.5
Awire|Vout|D5G1;||0|cap@0|a|6.5|-9.5|pin@9||4|-9.5
Awire|net@1|||900|cap@0|b|6.5|-13.5|gnd@0||6.5|-14.5
Awire|net@2|||1800|nmos@1|d|-1|-9.5|nmos@0|s|-0.5|-9.5
Awire|net@4|||1800|nmos@3|d|-10|-9.5|nmos@2|s|-9.5|-9.5
Awire|net@5|||1800|nmos@5|d|-19.5|-9.5|nmos@4|s|-19|-9.5
Awire|net@6|||1800|nmos@7|d|-28.5|-9.5|nmos@6|s|-28|-9.5
Awire|net@7|||1800|pin@14||-14.5|-9.5|nmos@3|s|-14|-9.5
Awire|net@9|||0|nmos@6|g|-26|-6.5|nmos@7|g|-30.5|-6.5
Awire|net@10|||1800|nmos@6|g|-26|-6.5|nmos@5|g|-21.5|-6.5
Awire|net@11|||1800|nmos@5|g|-21.5|-6.5|nmos@4|g|-17|-6.5
Awire|net@12|||1800|pin@7||-14.5|-6.5|nmos@3|g|-12|-6.5
Awire|net@13|||1800|nmos@3|g|-12|-6.5|nmos@2|g|-7.5|-6.5
Awire|net@14|||1800|nmos@2|g|-7.5|-6.5|nmos@1|g|-3|-6.5
Awire|net@15|||1800|nmos@1|g|-3|-6.5|nmos@0|g|1.5|-6.5
Awire|net@16|||1800|nmos@4|g|-17|-6.5|pin@7||-14.5|-6.5
Awire|net@17|||900|pwr@0||-14.5|-3.5|pin@7||-14.5|-6.5
Awire|net@18|||0|nmos@1|s|-5|-9.5|nmos@2|d|-5.5|-9.5
Awire|net@19|||0|nmos@5|s|-23.5|-9.5|nmos@6|d|-24|-9.5
Awire|net@20|||2700|gnd@1||-30.5|-15|pmos@0|g|-30.5|-14.5
Awire|net@21|||2700|gnd@2||-26|-15|pmos@1|g|-26|-14.5
Awire|net@22|||0|pmos@1|d|-28|-11.5|pmos@0|s|-28.5|-11.5
Awire|net@23|||2700|gnd@3||-21.5|-15|pmos@2|g|-21.5|-14.5
Awire|net@24|||2700|gnd@4||-17|-15|pmos@3|g|-17|-14.5
Awire|net@25|||0|pmos@3|d|-19|-11.5|pmos@2|s|-19.5|-11.5
Awire|net@26|||0|pmos@2|d|-23.5|-11.5|pmos@1|s|-24|-11.5
Awire|net@27|||2700|gnd@7||-3|-15|pmos@6|g|-3|-14.5
Awire|net@28|||2700|gnd@8||1.5|-15|pmos@7|g|1.5|-14.5
Awire|net@29|||0|pmos@7|d|-0.5|-11.5|pmos@6|s|-1|-11.5
Awire|net@30|||0|pmos@6|d|-5|-11.5|pmos@5|s|-5.5|-11.5
Awire|net@31|||2700|gnd@5||-12|-15|pmos@4|g|-12|-14.5
Awire|net@32|||2700|gnd@6||-7.5|-15|pmos@5|g|-7.5|-14.5
Awire|net@33|||0|pmos@5|d|-9.5|-11.5|pmos@4|s|-10|-11.5
Awire|net@34|||0|pin@15||-14.5|-11.5|pmos@3|s|-15|-11.5
Awire|net@35|||1800|pmos@7|s|3.5|-11.5|pin@8||4|-11.5
Awire|net@36|||0|pin@9||4|-9.5|nmos@0|d|3.5|-9.5
Awire|net@37|||2700|pin@8||4|-11.5|pin@9||4|-9.5
Awire|net@38|||0|pmos@0|d|-32.5|-11.5|pin@10||-33|-11.5
Awire|net@39|||0|nmos@7|s|-32.5|-9.5|pin@11||-33|-9.5
Awire|net@40|||2700|pin@10||-33|-11.5|pin@11||-33|-9.5
Awire|net@42|||2700|pmos@1|s|-24|-11.5|nmos@6|d|-24|-9.5
Awire|net@43|||1800|pmos@2|s|-19.5|-11.5|pin@13||-19|-11.5
Awire|net@44|||2700|pin@13||-19|-11.5|nmos@4|s|-19|-9.5
Awire|net@45|||1800|nmos@4|d|-15|-9.5|pin@14||-14.5|-9.5
Awire|net@46|||0|pmos@4|d|-14|-11.5|pin@15||-14.5|-11.5
Awire|net@47|||900|pin@14||-14.5|-9.5|pin@15||-14.5|-11.5
Awire|net@48|||900|nmos@2|s|-9.5|-9.5|pmos@5|d|-9.5|-11.5
Awire|net@49|||900|nmos@1|s|-5|-9.5|pmos@6|d|-5|-11.5
Awire|net@50|||900|nmos@1|d|-1|-9.5|pmos@6|s|-1|-11.5
Awire|net@51|||2700|pmos@0|s|-28.5|-11.5|nmos@7|d|-28.5|-9.5
X

# Cell Ex_6;1{sch}
CEx_6;1{sch}||schematic|1238524753678|1238709506122|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||6.5|-11.5|||||SCHEM_capacitance(D5G1;)S100f
NGround|gnd@0||6.5|-15.5|-2|-2||
NGround|gnd@1||-30.5|-16|-2|-2||
NGround|gnd@2||-26|-16|-2|-2||
NGround|gnd@3||-21.5|-16|-2|-2||
NGround|gnd@4||-17|-16|-2|-2||
NGround|gnd@5||-12|-16|-2|-2||
NGround|gnd@6||-7.5|-16|-2|-2||
NGround|gnd@7||-3|-16|-2|-2||
NGround|gnd@8||1.5|-16|-2|-2||
NTransistor|nmos@0||1.5|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@1||-3|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@2||-7.5|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@3||-12|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@4||-17|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@5||-21.5|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@6||-26|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@7||-30.5|-7.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Invisible-Pin|pin@2||-26.5|-2|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vin Vin 0 DC 0 PULSE 0 5 0 1p 1p 15n 30n,.tran 10p 100n]
NWire_Pin|pin@6||-34|-9.5||||
NWire_Pin|pin@7||-14.5|-6.5||||
NWire_Pin|pin@8||4|-11.5||||
NWire_Pin|pin@9||4|-9.5||||
NWire_Pin|pin@10||-33|-11.5||||
NWire_Pin|pin@11||-33|-9.5||||
NWire_Pin|pin@13||-19|-11.5||||
NWire_Pin|pin@14||-14.5|-9.5||||
NWire_Pin|pin@15||-14.5|-11.5||||
NTransistor|pmos@0||-30.5|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@1||-26|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@2||-21.5|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@3||-17|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@4||-12|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@5||-7.5|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@6||-3|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@7||1.5|-13.5|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||-14.5|-3.5||||
Awire|Vin|D5G1;||0|pin@11||-33|-9.5|pin@6||-34|-9.5
Awire|Vout|D5G1;||0|cap@0|a|6.5|-9.5|pin@9||4|-9.5
Awire|net@1|||900|cap@0|b|6.5|-13.5|gnd@0||6.5|-14.5
Awire|net@2|||1800|nmos@1|d|-1|-9.5|nmos@0|s|-0.5|-9.5
Awire|net@4|||1800|nmos@3|d|-10|-9.5|nmos@2|s|-9.5|-9.5
Awire|net@5|||1800|nmos@5|d|-19.5|-9.5|nmos@4|s|-19|-9.5
Awire|net@6|||1800|nmos@7|d|-28.5|-9.5|nmos@6|s|-28|-9.5
Awire|net@7|||1800|pin@14||-14.5|-9.5|nmos@3|s|-14|-9.5
Awire|net@9|||0|nmos@6|g|-26|-6.5|nmos@7|g|-30.5|-6.5
Awire|net@10|||1800|nmos@6|g|-26|-6.5|nmos@5|g|-21.5|-6.5
Awire|net@11|||1800|nmos@5|g|-21.5|-6.5|nmos@4|g|-17|-6.5
Awire|net@12|||1800|pin@7||-14.5|-6.5|nmos@3|g|-12|-6.5
Awire|net@13|||1800|nmos@3|g|-12|-6.5|nmos@2|g|-7.5|-6.5
Awire|net@14|||1800|nmos@2|g|-7.5|-6.5|nmos@1|g|-3|-6.5
Awire|net@15|||1800|nmos@1|g|-3|-6.5|nmos@0|g|1.5|-6.5
Awire|net@16|||1800|nmos@4|g|-17|-6.5|pin@7||-14.5|-6.5
Awire|net@17|||900|pwr@0||-14.5|-3.5|pin@7||-14.5|-6.5
Awire|net@18|||0|nmos@1|s|-5|-9.5|nmos@2|d|-5.5|-9.5
Awire|net@19|||0|nmos@5|s|-23.5|-9.5|nmos@6|d|-24|-9.5
Awire|net@20|||2700|gnd@1||-30.5|-15|pmos@0|g|-30.5|-14.5
Awire|net@21|||2700|gnd@2||-26|-15|pmos@1|g|-26|-14.5
Awire|net@22|||0|pmos@1|d|-28|-11.5|pmos@0|s|-28.5|-11.5
Awire|net@23|||2700|gnd@3||-21.5|-15|pmos@2|g|-21.5|-14.5
Awire|net@24|||2700|gnd@4||-17|-15|pmos@3|g|-17|-14.5
Awire|net@25|||0|pmos@3|d|-19|-11.5|pmos@2|s|-19.5|-11.5
Awire|net@26|||0|pmos@2|d|-23.5|-11.5|pmos@1|s|-24|-11.5
Awire|net@27|||2700|gnd@7||-3|-15|pmos@6|g|-3|-14.5
Awire|net@28|||2700|gnd@8||1.5|-15|pmos@7|g|1.5|-14.5
Awire|net@29|||0|pmos@7|d|-0.5|-11.5|pmos@6|s|-1|-11.5
Awire|net@30|||0|pmos@6|d|-5|-11.5|pmos@5|s|-5.5|-11.5
Awire|net@31|||2700|gnd@5||-12|-15|pmos@4|g|-12|-14.5
Awire|net@32|||2700|gnd@6||-7.5|-15|pmos@5|g|-7.5|-14.5
Awire|net@33|||0|pmos@5|d|-9.5|-11.5|pmos@4|s|-10|-11.5
Awire|net@34|||0|pin@15||-14.5|-11.5|pmos@3|s|-15|-11.5
Awire|net@35|||1800|pmos@7|s|3.5|-11.5|pin@8||4|-11.5
Awire|net@36|||0|pin@9||4|-9.5|nmos@0|d|3.5|-9.5
Awire|net@37|||2700|pin@8||4|-11.5|pin@9||4|-9.5
Awire|net@38|||0|pmos@0|d|-32.5|-11.5|pin@10||-33|-11.5
Awire|net@39|||0|nmos@7|s|-32.5|-9.5|pin@11||-33|-9.5
Awire|net@40|||2700|pin@10||-33|-11.5|pin@11||-33|-9.5
Awire|net@42|||2700|pmos@1|s|-24|-11.5|nmos@6|d|-24|-9.5
Awire|net@43|||1800|pmos@2|s|-19.5|-11.5|pin@13||-19|-11.5
Awire|net@44|||2700|pin@13||-19|-11.5|nmos@4|s|-19|-9.5
Awire|net@45|||1800|nmos@4|d|-15|-9.5|pin@14||-14.5|-9.5
Awire|net@46|||0|pmos@4|d|-14|-11.5|pin@15||-14.5|-11.5
Awire|net@47|||900|pin@14||-14.5|-9.5|pin@15||-14.5|-11.5
Awire|net@48|||900|nmos@2|s|-9.5|-9.5|pmos@5|d|-9.5|-11.5
Awire|net@49|||900|nmos@1|s|-5|-9.5|pmos@6|d|-5|-11.5
Awire|net@50|||900|nmos@1|d|-1|-9.5|pmos@6|s|-1|-11.5
Awire|net@51|||2700|pmos@0|s|-28.5|-11.5|nmos@7|d|-28.5|-9.5
X

# Cell Ex_7;1{sch}
CEx_7;1{sch}||schematic|1238524753678|1238710118863|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||15|1|||||SCHEM_capacitance(D5G1;)S100f
NGround|gnd@0||15|-1.5|-2|-2||
NGround|gnd@9||11|-3|-2|-2||
NTransistor|nmos@7||9|0.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Invisible-Pin|pin@2||-1|10|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vin Vin 0 DC 0 PULSE 0 5 0 1p 1p 3n 10n,.tran 10p 30n]
NWire_Pin|pin@6||3.5|3||||
NWire_Pin|pin@17||11|3||||
NWire_Pin|pin@18||7|5.5||||
NWire_Pin|pin@19||7|0.5||||
NWire_Pin|pin@20||7|3||||
NTransistor|pmos@0||9|5.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||11|10||||
Awire|Vin|D5G1;||1800|pin@6||3.5|3|pin@20||7|3
Awire|Vout|D5G1;||0|cap@0|a|15|3|pin@17||11|3
Awire|net@1|||2700|cap@0|b|15|-1|gnd@0||15|-0.5
Awire|net@53|||900|pin@17||11|3|nmos@7|d|11|2.5
Awire|net@54|||900|pwr@0||11|10|pmos@0|d|11|7.5
Awire|net@55|||2700|gnd@9||11|-2|nmos@7|s|11|-1.5
Awire|net@57|||900|pmos@0|s|11|3.5|pin@17||11|3
Awire|net@59|||0|pmos@0|g|8|5.5|pin@18||7|5.5
Awire|net@60|||900|pin@20||7|3|pin@19||7|0.5
Awire|net@61|||1800|pin@19||7|0.5|nmos@7|g|8|0.5
Awire|net@63|||900|pin@18||7|5.5|pin@20||7|3
X

# Cell Ex_8;1{sch}
CEx_8;1{sch}||schematic|1238524753678|1238710702030|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||22|0.5|||||SCHEM_capacitance(D5G1;)S100f
NGround|gnd@0||22|-2|-2|-2||
NGround|gnd@9||11|-3|-2|-2||
NGround|gnd@10||17|-3|-2|-2||
NTransistor|nmos@7||9|0.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@8||15|0.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D30.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Invisible-Pin|pin@2||14.5|-6.5|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vin Vin 0 DC 0 PULSE 0 5 0 1p 1p 3n 10n,.tran 10p 30n]
NWire_Pin|pin@6||3.5|3||||
NWire_Pin|pin@18||7|5.5||||
NWire_Pin|pin@19||7|0.5||||
NWire_Pin|pin@20||7|3||||
NWire_Pin|pin@21||17|2.5||||
NWire_Pin|pin@22||11|3||||
NWire_Pin|pin@23||14|3||||
NTransistor|pmos@0||9|5.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@1||15|5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D100.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||11|9||||
NPower|pwr@1||17|9||||
Awire|Vin|D5G1;||1800|pin@6||3.5|3|pin@20||7|3
Awire|Vout|D5G1;||0|cap@0|a|22|2.5|pin@21||17|2.5
Awire|n1|D5G1;||1800|pin@22||11|3|pin@23||14|3
Awire|net@1|||2700|cap@0|b|22|-1.5|gnd@0||22|-1
Awire|net@54|||900|pwr@0||11|9|pmos@0|d|11|7.5
Awire|net@55|||2700|gnd@9||11|-2|nmos@7|s|11|-1.5
Awire|net@59|||0|pmos@0|g|8|5.5|pin@18||7|5.5
Awire|net@60|||900|pin@20||7|3|pin@19||7|0.5
Awire|net@61|||1800|pin@19||7|0.5|nmos@7|g|8|0.5
Awire|net@63|||900|pin@18||7|5.5|pin@20||7|3
Awire|net@64|||2700|pin@22||11|3|pmos@0|s|11|3.5
Awire|net@65|||900|pwr@1||17|9|pmos@1|d|17|7
Awire|net@66|||2700|gnd@10||17|-2|nmos@8|s|17|-1.5
Awire|net@67|||2700|pin@21||17|2.5|pmos@1|s|17|3
Awire|net@68|||2700|nmos@8|d|17|2.5|pin@21||17|2.5
Awire|net@70|||2700|nmos@8|g|14|0.5|pin@23||14|3
Awire|net@71|||2700|nmos@7|d|11|2.5|pin@22||11|3
Awire|net@72|||2700|pin@23||14|3|pmos@1|g|14|5
X

# Cell Ideal_op_amp;1{ic}
CIdeal_op_amp;1{ic}||artwork|1181873067453|1206201690052|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Polygon|art@2||0|0.25|6|6.5|||trace()V[-3/-3.25,-3/3.25,3/-0.25,-3/-3.25]
Nschematic:Bus_Pin|pin@0||5|0||||
Nschematic:Wire_Pin|pin@1||3|0||||
Nschematic:Bus_Pin|pin@2||-5|1.75||||
Nschematic:Wire_Pin|pin@3||-3|1.75||||
Nschematic:Bus_Pin|pin@4||-5|-1.5||||
Nschematic:Wire_Pin|pin@5||-3|-1.5||||
Ngeneric:Invisible-Pin|pin@6||-2.25|2.5|||||ART_message(D5G1.5;)S_
Ngeneric:Invisible-Pin|pin@7||-2.25|-1.5|||||ART_message(D5G1.5;)S+
Ngeneric:Invisible-Pin|pin@8||-0.5|0.25|||||ART_message(D5G1;)SIdeal
Aschematic:wire|net@0|||1800|pin@1||3|0|pin@0||5|0
Aschematic:wire|net@1|||0|pin@3||-3|1.75|pin@2||-5|1.75
Aschematic:wire|net@2|||0|pin@5||-3|-1.5|pin@4||-5|-1.5
EOut||D5G2;|pin@0||O
EVinm||D5G1;|pin@2||I
EVinp||D5G1;|pin@4||I
X

# Cell Ideal_op_amp;1{sch}
CIdeal_op_amp;1{sch}||schematic|1181872798703|1182963267046|
IIdeal_op_amp;1{ic}|Ideal_op@0||19|13|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||-4.25|5.5||||
NOff-Page|conn@1||-4.25|-1.75||||
NOff-Page|conn@2||11|5.5||||
NGround|gnd@0||6.25|-2||||
NWire_Pin|pin@0||2|5.5||||
NWire_Pin|pin@1||2|-1.75||||
NWire_Pin|pin@2||6.25|5.5||||
Ngeneric:Invisible-Pin|pin@3||4|8|||||SIM_spice_card(D5G1;)SG1 Out 0 Vinm Vinp 1MEG
NResistor|res@0||2|1.5|||R||SCHEM_resistance(D5G1;X0.25;Y3;)S100Gohm
NResistor|res@1||6.25|2.5|||R||SCHEM_resistance(D5G1;X-0.25;Y-2.25;)S1ohm
Awire|net@0|||1800|conn@0|y|-2.25|5.5|pin@0||2|5.5
Awire|net@1|||900|pin@0||2|5.5|res@0|b|2|3.5
Awire|net@2|||900|res@0|a|2|-0.5|pin@1||2|-1.75
Awire|net@3|||0|pin@1||2|-1.75|conn@1|y|-2.25|-1.75
Awire|net@4|||2700|gnd@0||6.25|0|res@1|a|6.25|0.5
Awire|net@5|||2700|res@1|b|6.25|4.5|pin@2||6.25|5.5
Awire|net@6|||1800|pin@2||6.25|5.5|conn@2|a|9|5.5
EOut||D5G2;X2;|conn@2|y|O
EVinm||D5G2;X-2.5;|conn@1|a|I
EVinp||D5G2;X-2;|conn@0|a|I
X

# Cell NAND;1{ic}
CNAND;1{ic}||artwork|1235677085379|1235677449124|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NCircle|art@2||1.25|1|6|6|2850||ART_degrees()F[0.0,2.6179938]
NCircle|art@3||4.75|1|1|1||
NOpened-Polygon|art@5||-0.5|1|5|6|||trace()V[2.5/-3,-2.5/-3,-2.5/3,2.5/3]
Nschematic:Bus_Pin|pin@0||-4|3||||
Nschematic:Wire_Pin|pin@1||-3|3||||
Nschematic:Bus_Pin|pin@2||-4|-1||||
Nschematic:Wire_Pin|pin@3||-3|-1||||
Nschematic:Bus_Pin|pin@4||6.25|1|||RR|
Nschematic:Wire_Pin|pin@5||5.25|1|||RR|
Aschematic:wire|net@0|||0|pin@1||-3|3|pin@0||-4|3
Aschematic:wire|net@1|||0|pin@3||-3|-1|pin@2||-4|-1
Aschematic:wire|net@2|||1800|pin@5||5.25|1|pin@4||6.25|1
EA||D5G2;|pin@0||U
EB||D5G2;|pin@2||U
ENANDAB||D5G2;|pin@4||U
X

# Cell NAND;1{sch}
CNAND;1{sch}||schematic|1235676304307|1235677393585|
INAND;1{ic}|NAND@0||19.5|18|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@2||-3|4.25||||
NOff-Page|conn@3||-3|9||||
NOff-Page|conn@4||12.5|11.75||||
NGround|gnd@0||4.25|-0.25||||
NTransistor|nmos@0||2.25|4.25|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@1||2.25|9|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NWire_Pin|pin@2||4.25|11.75||||
NWire_Pin|pin@3||8.5|11.75||||
NWire_Pin|pin@5||2.75|11.75||||
NWire_Pin|pin@6||-0.25|9||||
NWire_Pin|pin@7||5.5|4.25||||
NTransistor|pmos@0||6.5|15|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1.25;Y-1.5;)SPMOS
NTransistor|pmos@1||0.75|15|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1.25;Y-1.5;)SPMOS
NPower|pwr@0||8.5|19.25||||
NPower|pwr@1||2.75|19.25||||
Awire|net@5|||2700|gnd@0||4.25|1.75|nmos@0|s|4.25|2.25
Awire|net@6|||900|pwr@0||8.5|19.25|pmos@0|d|8.5|17
Awire|net@13|||900|nmos@1|s|4.25|7|nmos@0|d|4.25|6.25
Awire|net@14|||1800|conn@2|y|-1|4.25|nmos@0|g|1.25|4.25
Awire|net@15|||1800|pin@6||-0.25|9|nmos@1|g|1.25|9
Awire|net@16|||900|pwr@1||2.75|19.25|pmos@1|d|2.75|17
Awire|net@17|||2700|nmos@1|d|4.25|11|pin@2||4.25|11.75
Awire|net@18|||1800|pin@2||4.25|11.75|pin@3||8.5|11.75
Awire|net@21|||0|pin@2||4.25|11.75|pin@5||2.75|11.75
Awire|net@22|||2700|pin@5||2.75|11.75|pmos@1|s|2.75|13
Awire|net@23|||1800|conn@3|y|-1|9|pin@6||-0.25|9
Awire|net@24|||900|pmos@1|g|-0.25|15|pin@6||-0.25|9
Awire|net@25|||900|pmos@0|g|5.5|15|pin@7||5.5|4.25
Awire|net@28|||2700|pin@3||8.5|11.75|pmos@0|s|8.5|13
Awire|net@29|||0|pin@7||5.5|4.25|nmos@0|g|1.25|4.25
Awire|net@30|||0|conn@4|a|10.5|11.75|pin@3||8.5|11.75
EA||D5G2;X1;|conn@3|a|U
EB||D5G2;X1;|conn@2|a|U
ENANDAB||D5G1;X-1.75;|conn@4|y|U
X

# Cell RC;1{sch}
CRC;1{sch}||schematic|1233950273136|1233950542164|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||13|6|||||SCHEM_capacitance(D5G1;X3;)S15p
NGround|gnd@0||13|0||||
NWire_Pin|pin@0||13|10||||
NWire_Pin|pin@1||5|10||||
Ngeneric:Invisible-Pin|pin@2||-1|5|||||SIM_spice_card(D5G1;)S[Vc Vc 0 DC 0 PULSE 0 1 200p 50p 50p 200p 500p,.tran 1p 2n]
Awire|Vc|D5G1;||0|pin@0||13|10|pin@1||5|10
Awire|net@0|||900|cap@0|b|13|4|gnd@0||13|2
Awire|net@1|||2700|cap@0|a|13|8|pin@0||13|10
X

# Cell RC1;1{sch}
CRC1;1{sch}||schematic|1232651928778|1232653267506|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||12|3|||||SCHEM_capacitance(D5G1;X3;)S1u
NGround|gnd@0||12|-3||||
NWire_Pin|pin@0||12|7||||
NWire_Pin|pin@2||-3|7||||
Ngeneric:Invisible-Pin|pin@3||0|3|||||SIM_spice_card(D5G1;)S[.tran 1u 5m,Vin Vin 0 DC 0  pulse 0 1 1m 1u 1u 10m 20m]
NResistor|res@0||4|7|||||SCHEM_resistance(D5G1;Y1;)S1k
Awire|VIn|D5G1;Y1;||0|res@0|a|2|7|pin@2||-3|7
Awire|net@0|||900|cap@0|b|12|1|gnd@0||12|-1
Awire|net@2|||900|pin@0||12|7|cap@0|a|12|5
Awire|out|D5G1;Y1;||1800|res@0|b|6|7|pin@0||12|7
X

# Cell RC_ex;1{sch}
CRC_ex;1{sch}||schematic|1236111707687|1236111855063|
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||8.5|-5||||
NTransistor|nmos@0||8.5|0|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D333.0|ATTR_width(D5G1;X0.5;Y-1;)D333.0|SIM_spice_model(D5G1;)SNMOS
NWire_Pin|pin@0||8.5|2||||
NWire_Pin|pin@1||6.5|-3||||
NWire_Pin|pin@2||10.5|-3||||
NWire_Pin|pin@3||-0.5|2||||
Ngeneric:Invisible-Pin|pin@4||11|5.5|||||SIM_spice_card(D5G1;)S[.include c5_models.txt,vgnd gnd 0 DC 0,Vin Vin 0 DC 0 Pulse 0 5 100n 1n,.tran 100p 2u 0 100p]
NResistor|res@0||4|2|||||SCHEM_resistance(D5G1;)S10k
Awire|Vin|D5G1;||0|res@0|a|2|2|pin@3||-0.5|2
Awire|Vout|D5G1;||0|pin@0||8.5|2|res@0|b|6|2
Awire|net@0|||2700|nmos@0|g|8.5|1|pin@0||8.5|2
Awire|net@2|||900|nmos@0|s|6.5|-2|pin@1||6.5|-3
Awire|net@3|||1800|pin@1||6.5|-3|gnd@0||8.5|-3
Awire|net@4|||900|nmos@0|d|10.5|-2|pin@2||10.5|-3
Awire|net@5|||0|pin@2||10.5|-3|gnd@0||8.5|-3
X

# Cell RC_pulse;1{sch}
CRC_pulse;1{sch}||schematic|1232482020262|1232482023060|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||7.75|3|||||SCHEM_capacitance(D5G1;X2.75;)S1pF
NGround|gnd@0||7.75|-3.5||||
NWire_Pin|pin@0||-4|7.75||||
NWire_Pin|pin@1||7.75|7.75||||
Ngeneric:Invisible-Pin|pin@2||-5|5.25|||||SIM_spice_card(D5G1;)SVin Vin 0 DC 0 AC 1 PULSE(-1 -2 2n 10p)
Ngeneric:Invisible-Pin|pin@3||0.25|1.75|||||SIM_spice_card(D5G1;)S[VGND GND 0 DC 0,.options post,.tran 1p 8n]
Ngeneric:Invisible-Pin|pin@4||2.25|11|||||ART_message(D5G2;)SPlot V(Vin) and V(vout)
NResistor|res@0||3|7.75|||||SCHEM_resistance(D5G1;X-0.25;Y1.25;)S1kohm
Awire|Vin|D5G1;X-0.5;Y0.75;||0|res@0|a|1|7.75|pin@0||-4|7.75
Awire|Vout|D5G1;X0.25;Y0.75;||1800|res@0|b|5|7.75|pin@1||7.75|7.75
Awire|net@0|||2700|cap@0|a|7.75|5|pin@1||7.75|7.75
Awire|net@1|||900|cap@0|b|7.75|1|gnd@0||7.75|-1.5
X

# Cell Rn_delay;1{sch}
CRn_delay;1{sch}||schematic|1238524753678|1238525562783|
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||14|1.5|-2|-2||
NTransistor|nmos@0||12|5.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NWire_Pin|pin@0||7|5.5||||
NWire_Pin|pin@1||14|10||||
Ngeneric:Invisible-Pin|pin@2||24.5|8|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,Vin Vin 0 DC 0 PULSE 0 5 5n 10p,.ic V(VDS)= 5,Cl VDS 0 1pF,.tran 10p 30n UIC]
Awire|VDS|D5G1;||2700|nmos@0|d|14|7.5|pin@1||14|10
Awire|Vin|D5G1;||0|nmos@0|g|11|5.5|pin@0||7|5.5
Awire|net@0|||2700|gnd@0||14|2.5|nmos@0|s|14|3.5
X

# Cell Rn_switch;1{sch}
CRn_switch;1{sch}||schematic|1238524753678|1238524952515|
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||14|1.5|-2|-2||
NTransistor|nmos@0||12|5.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NWire_Pin|pin@0||7|5.5||||
NWire_Pin|pin@1||14|10||||
Ngeneric:Invisible-Pin|pin@2||21|8|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,VDS VDS 0 DC 0,.DC VDS 0 5 1m]
Awire|VDD|D5G1;||0|nmos@0|g|11|5.5|pin@0||7|5.5
Awire|VDS|D5G1;||2700|nmos@0|d|14|7.5|pin@1||14|10
Awire|net@0|||2700|gnd@0||14|2.5|nmos@0|s|14|3.5
X

# Cell Rp_delay;1{sch}
CRp_delay;1{sch}||schematic|1238524753678|1238526107187|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||12.5|1|||||SCHEM_capacitance(D5G1;X2.5;)S1p
NGround|gnd@2||12.5|-3.5||||
Ngeneric:Invisible-Pin|pin@2||23|5.5|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vin Vin 0 DC 0 PULSE 5 0 5n 100p,.ic V(Vout)=0,.tran 10p 30n UIC]
NWire_Pin|pin@9||3.5|6.5||||
NTransistor|pmos@0||10.5|6.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||12.5|11||||
Awire|Vin|D5G1;||0|pmos@0|g|9.5|6.5|pin@9||3.5|6.5
Awire|Vout|D5G1;||2700|cap@0|a|12.5|3|pmos@0|s|12.5|4.5
Awire|net@11|||900|pwr@0||12.5|11|pmos@0|d|12.5|8.5
Awire|net@13|||2700|gnd@2||12.5|-1.5|cap@0|b|12.5|-1
X

# Cell Rp_switch;1{sch}
CRp_switch;1{sch}||schematic|1238524753678|1238525859239|
Ispiceparts:DCVoltage;1{ic}|VSD|D5G1;X3.5;|17|4.5|||D5G4;|ATTR_Voltage(D5G0.5;NP)S0V
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@1||7.5|4||||
Ngeneric:Invisible-Pin|pin@2||25.5|8.5|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,.DC VVSD 0 5 1m]
NWire_Pin|pin@3||9.5|6||||
NWire_Pin|pin@5||17|9||||
NWire_Pin|pin@6||12.5|9||||
NWire_Pin|pin@7||17|-0.5||||
NWire_Pin|pin@8||12.5|-0.5||||
NTransistor|pmos@0||10.5|6.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||12.5|11||||
Awire|VD|D5G1;||0|pin@7||17|-0.5|pin@8||12.5|-0.5
Awire|net@1|||2700|pin@6||12.5|9|pwr@0||12.5|11
Awire|net@2|||1800|gnd@1||7.5|6|pin@3||9.5|6
Awire|net@3|||2700|pin@3||9.5|6|pmos@0|g|9.5|6.5
Awire|net@5|||2700|VSD|plus|17|8|pin@5||17|9
Awire|net@6|||2700|pmos@0|d|12.5|8.5|pin@6||12.5|9
Awire|net@7|||0|pin@5||17|9|pin@6||12.5|9
Awire|net@8|||900|VSD|minus|17|1|pin@7||17|-0.5
Awire|net@10|||2700|pin@8||12.5|-0.5|pmos@0|s|12.5|4.5
X

# Cell box;1{lay}
Cbox;1{lay}||mocmos|1232482182368|1232482231926|
Ngeneric:Facet-Center|art@0||0|0||||AV
NN-Well-Node|plnode@0||0|0|60|10||A
X

# Cell bus_example;1{lay}
Cbus_example;1{lay}||mocmos|1240512335536|1240512392354|
Ngeneric:Facet-Center|art@0||0|0||||AV
X

# Cell bus_example;1{sch}
Cbus_example;1{sch}||schematic|1240512405519|1240512802564|
Iinv_20_10;1{ic}|Inv[0:31]|D5G1;X1;Y2.5;|-5.5|4.5|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NBus_Pin|pin@0||14|5||||
Abus|T0[0:15,32:47]|D5G1;||IJ0|pin@0||14|5|Inv[0:31]|Anot|4|5
X

# Cell cap;1{lay}
Ccap;1{lay}||mocmos|1235073467302|1235073723721|
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-Polysilicon-1-Con|contact@0||-5|0.5||10||
NMetal-1-Polysilicon-2-Con|contact@3||36.5|0||||
NPolysilicon-1-Pin|pin@0||22.5|0.5||||
NMetal-1-Pin|pin@3||-25|0.5||||
NPolysilicon-2-Pin|pin@7||12.5|0||||
APolysilicon-1|net@1||18|IJS0|pin@0||22.5|0.5|contact@0||-5|0.5
AMetal-1|net@3|||S0|contact@0||-5|0.5|pin@3||-25|0.5
APolysilicon-2|net@7|||S1800|pin@7||12.5|0|contact@3||36.5|0
X

# Cell comp_1;1{sch}
Ccomp_1;1{sch}||schematic|1239907564285|1239907891521|
NTransistor|M1|D5G1;Y-2.5;|-2.5|7.5|||XR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M2|D5G1;Y-2.5;|3|7.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||-12|10|||||SCHEM_capacitance(D5G1;)S100f
NCapacitor|cap@1||11.5|10|||||SCHEM_capacitance(D5G1;)S100f
NGround|gnd@0||-4.5|1.5||||
NGround|gnd@1||5|1.5||||
NGround|gnd@2||-12|5||||
NGround|gnd@3||11.5|5||||
Ngeneric:Invisible-Pin|pin@0||0.5|-3.5|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,.ic v(VD1)=1.2 V(VD2)=1.1,.tran 10p 3n UIC]
NWire_Pin|pin@1||5|12.5||||
NWire_Pin|pin@2||-4.5|12.5||||
NWire_Pin|pin@3||-12|12.5||||
NWire_Pin|pin@4||11.5|12.5||||
NWire_Pin|pin@6||-1.5|12.5||||
NWire_Pin|pin@8||2|12.5||||
Awire|VD1|D5G1;||0|pin@2||-4.5|12.5|pin@3||-12|12.5
Awire|VD2|D5G1;||1800|pin@1||5|12.5|pin@4||11.5|12.5
Awire|net@0|||2700|gnd@0||-4.5|3.5|M1|s|-4.5|5.5
Awire|net@1|||2700|gnd@1||5|3.5|M2|s|5|5.5
Awire|net@2|||2700|M2|d|5|9.5|pin@1||5|12.5
Awire|net@3|||2700|M1|d|-4.5|9.5|pin@2||-4.5|12.5
Awire|net@4|||2700|gnd@2||-12|7|cap@0|b|-12|8
Awire|net@5|||2700|gnd@3||11.5|7|cap@1|b|11.5|8
Awire|net@7|||900|pin@3||-12|12.5|cap@0|a|-12|12
Awire|net@9|||900|pin@4||11.5|12.5|cap@1|a|11.5|12
Awire|net@12|||0|pin@6||-1.5|12.5|pin@2||-4.5|12.5
Awire|net@15|||1800|pin@8||2|12.5|pin@1||5|12.5
Awire|net@16|||3050|M2|g|2|7.5|pin@6||-1.5|12.5
Awire|net@17|||2350|M1|g|-1.5|7.5|pin@8||2|12.5
X

# Cell comp_2;1{sch}
Ccomp_2;1{sch}||schematic|1239907564285|1239908152481|
NTransistor|M1|D5G1;Y-2.5;|-2.5|7.5|||XR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M2|D5G1;Y-2.5;|3|7.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||-12|10|||||SCHEM_capacitance(D5G1;)S100f
NCapacitor|cap@1||11.5|10|||||SCHEM_capacitance(D5G1;)S100f
NGround|gnd@0||-4.5|1.5||||
NGround|gnd@1||5|1.5||||
NGround|gnd@2||-12|5||||
NGround|gnd@3||11.5|5||||
Ngeneric:Invisible-Pin|pin@0||0.5|-3.5|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,.ic v(VD1)=1.2 V(VD2)=1.1,.tran 10p 3n UIC]
NWire_Pin|pin@1||5|12.5||||
NWire_Pin|pin@2||-4.5|12.5||||
NWire_Pin|pin@3||-12|12.5||||
NWire_Pin|pin@4||11.5|12.5||||
NWire_Pin|pin@6||-1.5|12.5||||
NWire_Pin|pin@8||2|12.5||||
NWire_Pin|pin@9||0|17.5||||
NWire_Pin|pin@10||-3.5|14||||
NWire_Pin|pin@11||-4.5|14||||
NWire_Pin|pin@12||-1.5|14||||
NWire_Pin|pin@13||5|14||||
NTransistor|pmos@0||3|17.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@1||-2.5|17.5|||XR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||-4.5|23||||
NPower|pwr@1||5|23||||
Awire|VD1|D5G1;||0|pin@2||-4.5|12.5|pin@3||-12|12.5
Awire|VD2|D5G1;||1800|pin@1||5|12.5|pin@4||11.5|12.5
Awire|net@0|||2700|gnd@0||-4.5|3.5|M1|s|-4.5|5.5
Awire|net@1|||2700|gnd@1||5|3.5|M2|s|5|5.5
Awire|net@2|||2700|M2|d|5|9.5|pin@1||5|12.5
Awire|net@3|||2700|M1|d|-4.5|9.5|pin@2||-4.5|12.5
Awire|net@4|||2700|gnd@2||-12|7|cap@0|b|-12|8
Awire|net@5|||2700|gnd@3||11.5|7|cap@1|b|11.5|8
Awire|net@7|||900|pin@3||-12|12.5|cap@0|a|-12|12
Awire|net@9|||900|pin@4||11.5|12.5|cap@1|a|11.5|12
Awire|net@12|||0|pin@6||-1.5|12.5|pin@2||-4.5|12.5
Awire|net@15|||1800|pin@8||2|12.5|pin@1||5|12.5
Awire|net@16|||3050|M2|g|2|7.5|pin@6||-1.5|12.5
Awire|net@17|||2350|M1|g|-1.5|7.5|pin@8||2|12.5
Awire|net@18|||900|pin@11||-4.5|14|pin@2||-4.5|12.5
Awire|net@19|||900|pin@13||5|14|pin@1||5|12.5
Awire|net@20|||900|pwr@0||-4.5|23|pmos@1|d|-4.5|19.5
Awire|net@21|||900|pwr@1||5|23|pmos@0|d|5|19.5
Awire|net@22|||0|pmos@0|g|2|17.5|pin@9||0|17.5
Awire|net@23|||450|pin@9||0|17.5|pin@10||-3.5|14
Awire|net@24|||900|pmos@1|s|-4.5|15.5|pin@11||-4.5|14
Awire|net@25|||0|pin@10||-3.5|14|pin@11||-4.5|14
Awire|net@26|||900|pmos@1|g|-1.5|17.5|pin@12||-1.5|14
Awire|net@27|||900|pmos@0|s|5|15.5|pin@13||5|14
Awire|net@28|||1800|pin@12||-1.5|14|pin@13||5|14
X

# Cell comp_3;1{sch}
Ccomp_3;1{sch}||schematic|1239907564285|1239909872557|
NTransistor|M1|D5G1;Y-2.5;|-2.5|7.5|||XR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M2|D5G1;Y-2.5;|3|7.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M3|D5G1;Y-2;|-16.5|10|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M4|D5G1;Y-2.5;|-7|10|||XR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M5|D5G1;Y-2.5;|-15.5|2.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D200.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M6|D5G1;Y-2.5;|3|16|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M7|D5G1;Y-2.5;|-6.5|16|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||12|21||||
NOff-Page|conn@1||12|18.5||||
NOff-Page|conn@2||-20.5|10||||
NOff-Page|conn@3||-20.5|6.5||||
NOff-Page|conn@4||-19.5|16||||
NGround|gnd@0||-4.5|2.5||||
NGround|gnd@1||5|2.5||||
NGround|gnd@4||-13.5|-2.5||||
Ngeneric:Invisible-Pin|pin@0||13.5|12.5|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Iin1 0 Out DC 20u,Iin2 0 Outi DC 10u,.tran 10p 3n UIC]
NWire_Pin|pin@6||-1.5|12.5||||
NWire_Pin|pin@8||2|12.5||||
NWire_Pin|pin@9||0.5|23.5||||
NWire_Pin|pin@10||-2|21||||
NWire_Pin|pin@11||-4.5|21||||
NWire_Pin|pin@19||-13.5|8||||
NWire_Pin|pin@20||-6|6.5||||
NWire_Pin|pin@21||5|21||||
NWire_Pin|pin@22||-1.5|21||||
NWire_Pin|pin@24||-4.5|18.5||||
NWire_Pin|pin@25||-14.5|19.5||||
NWire_Pin|pin@27||5|19.5||||
NWire_Pin|pin@29||-9|18.5||||
NWire_Pin|pin@30||5|25.5||||
NWire_Pin|pin@31||6.5|21||||
NWire_Pin|pin@32||11.5|23.5||||
NWire_Pin|pin@33||-6.5|26||||
NWire_Pin|pin@34||-4.5|26||||
NWire_Pin|pin@35||-6.5|21||||
NWire_Pin|pin@36||-9.5|16||||
NWire_Pin|pin@37||2|19.5||||
NWire_Pin|pin@38||-1.5|18.5||||
NTransistor|pmos@0||3|23.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@1||-2.5|23.5|||XR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@2||8.5|23.5|||XR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@3||-8.5|23.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||-4.5|27.5||||
NPower|pwr@1||5|27.5||||
NPower|pwr@2||-18.5|2.5||||
Awire|clk|D5G1;||1800|pmos@2|g|9.5|23.5|pin@32||11.5|23.5
Awire|net@0|||2700|gnd@0||-4.5|4.5|M1|s|-4.5|5.5
Awire|net@1|||2700|gnd@1||5|4.5|M2|s|5|5.5
Awire|net@16|||3050|M2|g|2|7.5|pin@6||-1.5|12.5
Awire|net@17|||2350|M1|g|-1.5|7.5|pin@8||2|12.5
Awire|net@20|||900|pwr@0||-4.5|27.5|pmos@1|d|-4.5|25.5
Awire|net@21|||900|pwr@1||5|27.5|pmos@0|d|5|25.5
Awire|net@22|||0|pmos@0|g|2|23.5|pin@9||0.5|23.5
Awire|net@25|||0|pin@10||-2|21|pin@11||-4.5|21
Awire|net@40|||2700|gnd@4||-13.5|-0.5|M5|s|-13.5|0.5
Awire|net@41|||2700|M5|d|-13.5|4.5|pin@19||-13.5|8
Awire|net@42|||1800|pin@19||-13.5|8|M4|s|-9|8
Awire|net@43|||1800|M3|s|-14.5|8|pin@19||-13.5|8
Awire|net@44|||1800|conn@2|y|-18.5|10|M3|g|-17.5|10
Awire|net@45|||900|M4|g|-6|10|pin@20||-6|6.5
Awire|net@46|||0|pin@20||-6|6.5|conn@3|y|-18.5|6.5
Awire|net@47|||1800|pwr@2||-18.5|2.5|M5|g|-16.5|2.5
Awire|net@48|||1800|pin@31||6.5|21|conn@0|a|10|21
Awire|net@51|||900|pmos@0|s|5|21.5|pin@21||5|21
Awire|net@52|||900|pmos@1|s|-4.5|21.5|pin@11||-4.5|21
Awire|net@53|||450|pin@9||0.5|23.5|pin@10||-2|21
Awire|net@55|||2700|pin@22||-1.5|21|pmos@1|g|-1.5|23.5
Awire|net@57|||2700|pin@27||5|19.5|pin@21||5|21
Awire|net@62|||1800|conn@4|y|-17.5|16|pin@36||-9.5|16
Awire|net@63|||0|pin@21||5|21|pin@22||-1.5|21
Awire|net@64|||1800|M7|g|-7.5|16|M6|g|2|16
Awire|net@66|||2700|M7|d|-4.5|18|pin@24||-4.5|18.5
Awire|net@67|||0|conn@1|a|10|18.5|pin@38||-1.5|18.5
Awire|net@72|||900|pin@11||-4.5|21|pin@24||-4.5|18.5
Awire|net@73|||2700|M6|d|5|18|pin@27||5|19.5
Awire|net@74|||1800|pin@25||-14.5|19.5|pin@37||2|19.5
Awire|net@78|||1800|pin@29||-9|18.5|pin@24||-4.5|18.5
Awire|net@79|||2700|M3|d|-14.5|12|pin@25||-14.5|19.5
Awire|net@80|||2700|M4|d|-9|12|pin@29||-9|18.5
Awire|net@81|||900|M7|s|-4.5|14|M1|d|-4.5|9.5
Awire|net@82|||2700|M2|d|5|9.5|M6|s|5|14
Awire|net@83|||0|pmos@2|d|6.5|25.5|pin@30||5|25.5
Awire|net@84|||2700|pin@30||5|25.5|pwr@1||5|27.5
Awire|net@85|||1800|pin@21||5|21|pin@31||6.5|21
Awire|net@86|||900|pmos@2|s|6.5|21.5|pin@31||6.5|21
Awire|net@88|||2700|pmos@3|d|-6.5|25.5|pin@33||-6.5|26
Awire|net@89|||1800|pin@33||-6.5|26|pin@34||-4.5|26
Awire|net@90|||2700|pin@34||-4.5|26|pwr@0||-4.5|27.5
Awire|net@91|||900|pmos@3|s|-6.5|21.5|pin@35||-6.5|21
Awire|net@92|||1800|pin@35||-6.5|21|pin@11||-4.5|21
Awire|net@93|||1800|pin@36||-9.5|16|M7|g|-7.5|16
Awire|net@94|||900|pmos@3|g|-9.5|23.5|pin@36||-9.5|16
Awire|net@95|||1800|pin@37||2|19.5|pin@27||5|19.5
Awire|net@96|||2700|pin@8||2|12.5|pin@37||2|19.5
Awire|net@97|||0|pin@38||-1.5|18.5|pin@24||-4.5|18.5
Awire|net@98|||2700|pin@6||-1.5|12.5|pin@38||-1.5|18.5
EInm||D5G2;|conn@2|a|U
EInp||D5G2;|conn@3|a|U
EOuti|Outm|D5G2;|conn@1|y|U
EOut|Outp|D5G2;|conn@0|y|U
Eclk||D5G2;|conn@4|a|U
X

# Cell comp_4;1{sch}
Ccomp_4;1{sch}||schematic|1239907564285|1240339689137|
NTransistor|M1|D5G1;Y-2.5;|-3.5|7.5|||XR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M2|D5G1;Y-2.5;|3|7.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M6|D5G1;Y-2.5;|3|16|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M7|D5G1;Y-2.5;|-7.5|16|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M8|D5G1;Y-2.5;|-23.5|10.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M9|D5G1;Y-2.5;|-17|10.5|||XR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M10|D5G1;Y-2.5;|-22.5|4|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D5.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||-13|16||||
NOff-Page|conn@1||26.5|14.5||||
NOff-Page|conn@2||26.5|21||||
NOff-Page|conn@3||-27|10.5||||
NOff-Page|conn@4||-13|10.5|||RR|
NGround|gnd@0||-5.5|2.5||||
NGround|gnd@1||5|2.5||||
NGround|gnd@2||-20.5|-0.5||||
Iinv_20_10;1{ic}|inv_20_1@0||12|20.5|||D5G4;
Iinv_20_10;1{ic}|inv_20_1@1||12|14|||D5G4;
Ngeneric:Invisible-Pin|pin@0||-20|26|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vinp inp 0 DC 0 sin 2.5 1 1MEG,Vinm inm 0 DC 2.5,com outm 0 100f,cop outp 0 100f,vclk clk 0 DC 0 pulse 0 5 0 100p 100p 9.8n 20n,.tran 100p 2u UIC]
NWire_Pin|pin@6||-1.5|12.5||||
NWire_Pin|pin@8||1|12.5||||
NWire_Pin|pin@9||0.5|23.5||||
NWire_Pin|pin@10||-2|21||||
NWire_Pin|pin@11||-5.5|21||||
NWire_Pin|pin@21||5|21||||
NWire_Pin|pin@22||1|21||||
NWire_Pin|pin@24||-5.5|18.5||||
NWire_Pin|pin@27||5|19.5||||
NWire_Pin|pin@30||5|25.5||||
NWire_Pin|pin@31||6.5|21||||
NWire_Pin|pin@32||10.5|23.5||||
NWire_Pin|pin@33||-6.5|26||||
NWire_Pin|pin@34||-5.5|26||||
NWire_Pin|pin@35||-6.5|21||||
NWire_Pin|pin@36||-9.5|16||||
NWire_Pin|pin@37||1|19.5||||
NWire_Pin|pin@38||-1.5|18.5||||
NWire_Pin|pin@39||10.5|16||||
NWire_Pin|pin@40||-19|7.5||||
NWire_Pin|pin@41||-21.5|7.5||||
NWire_Pin|pin@42||-20.5|7.5||||
NWire_Pin|pin@43||-25|4||||
NWire_Pin|pin@46||-21.5|20.5||||
NWire_Pin|pin@47||-5.5|20.5||||
NWire_Pin|pin@48||-19|19.5||||
NWire_Pin|pin@50||8|14.5||||
NWire_Pin|pin@53||8|18.5||||
NTransistor|pmos@0||3|23.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@1||-3.5|23.5|||XR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@2||8.5|23.5|||XR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@3||-8.5|23.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||-5.5|27.5||||
NPower|pwr@1||5|27.5||||
NPower|pwr@2||-25|6||||
Awire|net@0|||2700|gnd@0||-5.5|4.5|M1|s|-5.5|5.5
Awire|net@1|||2700|gnd@1||5|4.5|M2|s|5|5.5
Awire|net@16|||3050|M2|g|2|7.5|pin@6||-1.5|12.5
Awire|net@17|||2350|M1|g|-2.5|7.5|pin@8||1|12.5
Awire|net@20|||900|pwr@0||-5.5|27.5|pmos@1|d|-5.5|25.5
Awire|net@21|||900|pwr@1||5|27.5|pmos@0|d|5|25.5
Awire|net@22|||0|pmos@0|g|2|23.5|pin@9||0.5|23.5
Awire|net@25|||0|pin@10||-2|21|pin@11||-5.5|21
Awire|net@51|||900|pmos@0|s|5|21.5|pin@21||5|21
Awire|net@52|||900|pmos@1|s|-5.5|21.5|pin@11||-5.5|21
Awire|net@53|||450|pin@9||0.5|23.5|pin@10||-2|21
Awire|net@55|||F3245|pin@22||1|21|pmos@1|g|-2.5|23.5
Awire|net@57|||2700|pin@27||5|19.5|pin@21||5|21
Awire|net@63|||0|pin@21||5|21|pin@22||1|21
Awire|net@64|||1800|M7|g|-8.5|16|M6|g|2|16
Awire|net@66|||2700|M7|d|-5.5|18|pin@24||-5.5|18.5
Awire|net@72|||900|pin@47||-5.5|20.5|pin@24||-5.5|18.5
Awire|net@73|||2700|M6|d|5|18|pin@27||5|19.5
Awire|net@81|||900|M7|s|-5.5|14|M1|d|-5.5|9.5
Awire|net@82|||2700|M2|d|5|9.5|M6|s|5|14
Awire|net@83|||0|pmos@2|d|6.5|25.5|pin@30||5|25.5
Awire|net@84|||2700|pin@30||5|25.5|pwr@1||5|27.5
Awire|net@85|||1800|pin@21||5|21|pin@31||6.5|21
Awire|net@86|||900|pmos@2|s|6.5|21.5|pin@31||6.5|21
Awire|net@88|||2700|pmos@3|d|-6.5|25.5|pin@33||-6.5|26
Awire|net@89|||1800|pin@33||-6.5|26|pin@34||-5.5|26
Awire|net@90|||2700|pin@34||-5.5|26|pwr@0||-5.5|27.5
Awire|net@91|||900|pmos@3|s|-6.5|21.5|pin@35||-6.5|21
Awire|net@92|||1800|pin@35||-6.5|21|pin@11||-5.5|21
Awire|net@93|||1800|pin@36||-9.5|16|M7|g|-8.5|16
Awire|net@94|||900|pmos@3|g|-9.5|23.5|pin@36||-9.5|16
Awire|net@95|||1800|pin@37||1|19.5|pin@27||5|19.5
Awire|net@96|||2700|pin@8||1|12.5|pin@37||1|19.5
Awire|net@97|||0|pin@38||-1.5|18.5|pin@24||-5.5|18.5
Awire|net@98|||2700|pin@6||-1.5|12.5|pin@38||-1.5|18.5
Awire|net@99|||1800|conn@0|y|-11|16|pin@36||-9.5|16
Awire|net@100|||1800|pmos@2|g|9.5|23.5|pin@32||10.5|23.5
Awire|net@101|||900|pin@32||10.5|23.5|pin@39||10.5|16
Awire|net@102|||0|pin@39||10.5|16|M6|g|2|16
Awire|net@105|||900|M9|s|-19|8.5|pin@40||-19|7.5
Awire|net@106|||0|pin@40||-19|7.5|pin@42||-20.5|7.5
Awire|net@107|||2700|pin@41||-21.5|7.5|M8|s|-21.5|8.5
Awire|net@108|||2700|gnd@2||-20.5|1.5|M10|s|-20.5|2
Awire|net@109|||0|pin@42||-20.5|7.5|pin@41||-21.5|7.5
Awire|net@110|||2700|M10|d|-20.5|6|pin@42||-20.5|7.5
Awire|net@111|||900|pwr@2||-25|6|pin@43||-25|4
Awire|net@112|||1800|pin@43||-25|4|M10|g|-23.5|4
Awire|net@113|||1800|conn@3|y|-25|10.5|M8|g|-24.5|10.5
Awire|net@114|||0|conn@4|y|-15|10.5|M9|g|-16|10.5
Awire|net@119|||900|pin@11||-5.5|21|pin@47||-5.5|20.5
Awire|net@120|||1800|pin@46||-21.5|20.5|pin@47||-5.5|20.5
Awire|net@121|||0|pin@37||1|19.5|pin@48||-19|19.5
Awire|net@122|||900|pin@48||-19|19.5|M9|d|-19|12.5
Awire|net@123|||2700|M8|d|-21.5|12.5|pin@46||-21.5|20.5
Awire|net@124|||0|inv_20_1@0|A|12.5|21|pin@31||6.5|21
Awire|net@127|||2700|pin@50||8|14.5|pin@53||8|18.5
Awire|net@130|||0|inv_20_1@1|A|12.5|14.5|pin@50||8|14.5
Awire|net@131|||0|conn@1|a|24.5|14.5|inv_20_1@1|Anot|21.5|14.5
Awire|net@132|||0|conn@2|a|24.5|21|inv_20_1@0|Anot|21.5|21
Awire|net@134|||1800|pin@38||-1.5|18.5|pin@53||8|18.5
Eclk||D5G2;X1.5;|conn@0|a|U
Einm||D5G2;|conn@4|a|U
Einp||D5G2;|conn@3|a|U
Eoutm||D5G2;|conn@2|y|U
Eoutp||D5G2;|conn@1|y|U
X

# Cell comp_5;1{sch}
Ccomp_5;1{sch}||schematic|1239907564285|1241119155059|
NTransistor|M1|D5G1;Y-2.5;|-3.5|7.5|||XR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M2|D5G1;Y-2.5;|3|7.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M6|D5G1;Y-2.5;|3|16|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M7|D5G1;Y-2.5;|-7.5|16|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M8|D5G1;Y-2.5;|-23.5|10.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M9|D5G1;Y-2.5;|-17|10.5|||XR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M10|D5G1;Y-2.5;|-22.5|4|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D5.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
INAND;1{ic}|NAND@0||22|18.5|||D5G4;
INAND;1{ic}|NAND@1||22|9|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||-13|16||||
NOff-Page|conn@1||34.5|10||||
NOff-Page|conn@2||34|19.5||||
NOff-Page|conn@3||-27|10.5||||
NOff-Page|conn@4||-13|10.5|||RR|
NGround|gnd@0||-5.5|2.5||||
NGround|gnd@1||5|2.5||||
NGround|gnd@2||-20.5|-0.5||||
Ngeneric:Invisible-Pin|pin@0||-20|26|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vinp inp 0 DC 0 sin 2.5 .5 1MEG,Vinm inm 0 DC 2.5,vclk clk 0 DC 0 pulse 0 5 0 100p 100p 9.8n 20n,.tran 100p 2u UIC]
NWire_Pin|pin@6||-1.5|12.5||||
NWire_Pin|pin@8||1|12.5||||
NWire_Pin|pin@9||0.5|23.5||||
NWire_Pin|pin@10||-2|21||||
NWire_Pin|pin@11||-5.5|21||||
NWire_Pin|pin@21||5|21||||
NWire_Pin|pin@22||1|21||||
NWire_Pin|pin@24||-5.5|18.5||||
NWire_Pin|pin@27||5|19.5||||
NWire_Pin|pin@30||5|25.5||||
NWire_Pin|pin@31||6.5|21||||
NWire_Pin|pin@32||10.5|23.5||||
NWire_Pin|pin@33||-6.5|26||||
NWire_Pin|pin@34||-5.5|26||||
NWire_Pin|pin@35||-6.5|21||||
NWire_Pin|pin@36||-9.5|16||||
NWire_Pin|pin@37||1|19.5||||
NWire_Pin|pin@38||-1.5|18.5||||
NWire_Pin|pin@39||10.5|16||||
NWire_Pin|pin@40||-19|7.5||||
NWire_Pin|pin@41||-21.5|7.5||||
NWire_Pin|pin@42||-20.5|7.5||||
NWire_Pin|pin@43||-25|4||||
NWire_Pin|pin@46||-21.5|20.5||||
NWire_Pin|pin@47||-5.5|20.5||||
NWire_Pin|pin@48||-19|19.5||||
NWire_Pin|pin@53||8|18.5||||
NWire_Pin|pin@58||16|17.5||||
NWire_Pin|pin@59||16|15||||
NWire_Pin|pin@60||28.5|15||||
NWire_Pin|pin@61||28.5|10||||
NWire_Pin|pin@62||30|19.5||||
NWire_Pin|pin@63||30|14||||
NWire_Pin|pin@64||15|14||||
NWire_Pin|pin@65||15|12.5||||
NWire_Pin|pin@66||18|12.5||||
NWire_Pin|pin@67||13.5|21.5||||
NWire_Pin|pin@68||13.5|20||||
NWire_Pin|pin@69||5|20||||
NWire_Pin|pin@71||8|8||||
NTransistor|pmos@0||3|23.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@1||-3.5|23.5|||XR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@2||8.5|23.5|||XR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@3||-8.5|23.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||-5.5|27.5||||
NPower|pwr@1||5|27.5||||
NPower|pwr@2||-25|6||||
Awire|net@0|||2700|gnd@0||-5.5|4.5|M1|s|-5.5|5.5
Awire|net@1|||2700|gnd@1||5|4.5|M2|s|5|5.5
Awire|net@16|||3050|M2|g|2|7.5|pin@6||-1.5|12.5
Awire|net@17|||2350|M1|g|-2.5|7.5|pin@8||1|12.5
Awire|net@20|||900|pwr@0||-5.5|27.5|pmos@1|d|-5.5|25.5
Awire|net@21|||900|pwr@1||5|27.5|pmos@0|d|5|25.5
Awire|net@22|||0|pmos@0|g|2|23.5|pin@9||0.5|23.5
Awire|net@25|||0|pin@10||-2|21|pin@11||-5.5|21
Awire|net@51|||900|pmos@0|s|5|21.5|pin@21||5|21
Awire|net@52|||900|pmos@1|s|-5.5|21.5|pin@11||-5.5|21
Awire|net@53|||450|pin@9||0.5|23.5|pin@10||-2|21
Awire|net@55|||F3245|pin@22||1|21|pmos@1|g|-2.5|23.5
Awire|net@57|||2700|pin@27||5|19.5|pin@21||5|21
Awire|net@63|||0|pin@21||5|21|pin@22||1|21
Awire|net@64|||1800|M7|g|-8.5|16|M6|g|2|16
Awire|net@66|||2700|M7|d|-5.5|18|pin@24||-5.5|18.5
Awire|net@72|||900|pin@47||-5.5|20.5|pin@24||-5.5|18.5
Awire|net@73|||2700|M6|d|5|18|pin@27||5|19.5
Awire|net@81|||900|M7|s|-5.5|14|M1|d|-5.5|9.5
Awire|net@82|||2700|M2|d|5|9.5|M6|s|5|14
Awire|net@83|||0|pmos@2|d|6.5|25.5|pin@30||5|25.5
Awire|net@84|||2700|pin@30||5|25.5|pwr@1||5|27.5
Awire|net@85|||1800|pin@21||5|21|pin@31||6.5|21
Awire|net@86|||900|pmos@2|s|6.5|21.5|pin@31||6.5|21
Awire|net@88|||2700|pmos@3|d|-6.5|25.5|pin@33||-6.5|26
Awire|net@89|||1800|pin@33||-6.5|26|pin@34||-5.5|26
Awire|net@90|||2700|pin@34||-5.5|26|pwr@0||-5.5|27.5
Awire|net@91|||900|pmos@3|s|-6.5|21.5|pin@35||-6.5|21
Awire|net@92|||1800|pin@35||-6.5|21|pin@11||-5.5|21
Awire|net@93|||1800|pin@36||-9.5|16|M7|g|-8.5|16
Awire|net@94|||900|pmos@3|g|-9.5|23.5|pin@36||-9.5|16
Awire|net@95|||1800|pin@37||1|19.5|pin@27||5|19.5
Awire|net@96|||2700|pin@8||1|12.5|pin@37||1|19.5
Awire|net@97|||0|pin@38||-1.5|18.5|pin@24||-5.5|18.5
Awire|net@98|||2700|pin@6||-1.5|12.5|pin@38||-1.5|18.5
Awire|net@99|||1800|conn@0|y|-11|16|pin@36||-9.5|16
Awire|net@100|||1800|pmos@2|g|9.5|23.5|pin@32||10.5|23.5
Awire|net@101|||900|pin@32||10.5|23.5|pin@39||10.5|16
Awire|net@102|||0|pin@39||10.5|16|M6|g|2|16
Awire|net@105|||900|M9|s|-19|8.5|pin@40||-19|7.5
Awire|net@106|||0|pin@40||-19|7.5|pin@42||-20.5|7.5
Awire|net@107|||2700|pin@41||-21.5|7.5|M8|s|-21.5|8.5
Awire|net@108|||2700|gnd@2||-20.5|1.5|M10|s|-20.5|2
Awire|net@109|||0|pin@42||-20.5|7.5|pin@41||-21.5|7.5
Awire|net@110|||2700|M10|d|-20.5|6|pin@42||-20.5|7.5
Awire|net@111|||900|pwr@2||-25|6|pin@43||-25|4
Awire|net@112|||1800|pin@43||-25|4|M10|g|-23.5|4
Awire|net@113|||1800|conn@3|y|-25|10.5|M8|g|-24.5|10.5
Awire|net@114|||0|conn@4|y|-15|10.5|M9|g|-16|10.5
Awire|net@119|||900|pin@11||-5.5|21|pin@47||-5.5|20.5
Awire|net@120|||1800|pin@46||-21.5|20.5|pin@47||-5.5|20.5
Awire|net@121|||0|pin@37||1|19.5|pin@48||-19|19.5
Awire|net@122|||900|pin@48||-19|19.5|M9|d|-19|12.5
Awire|net@123|||2700|M8|d|-21.5|12.5|pin@46||-21.5|20.5
Awire|net@134|||1800|pin@38||-1.5|18.5|pin@53||8|18.5
Awire|net@139|||0|NAND@0|B|18|17.5|pin@58||16|17.5
Awire|net@140|||900|pin@58||16|17.5|pin@59||16|15
Awire|net@141|||1800|pin@59||16|15|pin@60||28.5|15
Awire|net@142|||900|pin@60||28.5|15|pin@61||28.5|10
Awire|net@143|||0|pin@61||28.5|10|NAND@1|NANDAB|28.25|10
Awire|net@144|||1800|NAND@0|NANDAB|28.25|19.5|pin@62||30|19.5
Awire|net@145|||900|pin@62||30|19.5|pin@63||30|14
Awire|net@146|||0|pin@63||30|14|pin@64||15|14
Awire|net@147|||900|pin@64||15|14|pin@65||15|12.5
Awire|net@148|||1800|pin@65||15|12.5|pin@66||18|12.5
Awire|net@149|||900|pin@66||18|12.5|NAND@1|A|18|12
Awire|net@150|||0|NAND@0|A|18|21.5|pin@67||13.5|21.5
Awire|net@151|||900|pin@67||13.5|21.5|pin@68||13.5|20
Awire|net@152|||0|pin@68||13.5|20|pin@69||5|20
Awire|net@153|||900|pin@69||5|20|pin@27||5|19.5
Awire|net@157|||0|conn@1|a|32.5|10|pin@61||28.5|10
Awire|net@158|||0|conn@2|a|32|19.5|pin@62||30|19.5
Awire|net@159|||900|pin@53||8|18.5|pin@71||8|8
Awire|net@160|||0|NAND@1|B|18|8|pin@71||8|8
Eclk||D5G2;X1.5;|conn@0|a|U
Einm||D5G2;|conn@4|a|U
Einp||D5G2;|conn@3|a|U
Eoutm||D5G2;|conn@2|y|U
Eoutp||D5G2;|conn@1|y|U
X

# Cell comp_6;1{sch}
Ccomp_6;1{sch}||schematic|1239907564285|1241119323664|
NTransistor|M1|D5G1;Y-2.5;|-3.5|7.5|||XR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M2|D5G1;Y-2.5;|3|7.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M6|D5G1;Y-2.5;|3|15|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M7|D5G1;Y-2.5;|-7.5|15|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M8|D5G1;Y-2.5;|-23.5|10.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M9|D5G1;Y-2.5;|-17|10.5|||XR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M10|D5G1;Y-2.5;|-22.5|4|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D5.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|M11|D5G1;Y-2.5;|14|16|||RR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||17.5|15|||||SCHEM_capacitance(D5G1;)S10f
NOff-Page|conn@0||-13|15||||
NOff-Page|conn@2||21.5|18||||
NOff-Page|conn@3||-27|10.5||||
NOff-Page|conn@4||-13|10.5|||RR|
NGround|gnd@0||-5.5|2.5||||
NGround|gnd@1||5|2.5||||
NGround|gnd@2||-20.5|-0.5||||
NGround|gnd@3||17.5|9.5||||
NWire_Pin|pin@6||-1.5|12.5||||
NWire_Pin|pin@8||1|12.5||||
NWire_Pin|pin@9||0.5|23.5||||
NWire_Pin|pin@10||-2|21||||
NWire_Pin|pin@11||-5.5|21||||
NWire_Pin|pin@21||5|21||||
NWire_Pin|pin@22||1|21||||
NWire_Pin|pin@24||-5.5|18.5||||
NWire_Pin|pin@27||5|19.5||||
NWire_Pin|pin@30||5|25.5||||
NWire_Pin|pin@31||6.5|21||||
NWire_Pin|pin@32||10.5|23.5||||
NWire_Pin|pin@33||-6.5|26||||
NWire_Pin|pin@34||-5.5|26||||
NWire_Pin|pin@35||-6.5|21||||
NWire_Pin|pin@36||-9.5|15||||
NWire_Pin|pin@37||1|19.5||||
NWire_Pin|pin@38||-1.5|18.5||||
NWire_Pin|pin@39||10.5|15||||
NWire_Pin|pin@40||-19|7.5||||
NWire_Pin|pin@41||-21.5|7.5||||
NWire_Pin|pin@42||-20.5|7.5||||
NWire_Pin|pin@43||-25|4||||
NWire_Pin|pin@46||-21.5|20.5||||
NWire_Pin|pin@47||-5.5|20.5||||
NWire_Pin|pin@48||-19|19.5||||
NWire_Pin|pin@72||5|18||||
NWire_Pin|pin@73||17.5|18||||
Ngeneric:Invisible-Pin|pin@74||-21.5|25.5|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vinp inp 0 DC 0 sin 2.5 .5 1MEG,Vinm inm 0 DC 2.5,vclk clk 0 DC 0 pulse 0 5 0 100p 100p 9.8n 20n,.tran 100p 2u UIC]
NTransistor|pmos@0||3|23.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@1||-3.5|23.5|||XR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@2||8.5|23.5|||XR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@3||-8.5|23.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||-5.5|27.5||||
NPower|pwr@1||5|27.5||||
NPower|pwr@2||-25|6||||
Awire|net@0|||2700|gnd@0||-5.5|4.5|M1|s|-5.5|5.5
Awire|net@1|||2700|gnd@1||5|4.5|M2|s|5|5.5
Awire|net@16|||3050|M2|g|2|7.5|pin@6||-1.5|12.5
Awire|net@17|||2350|M1|g|-2.5|7.5|pin@8||1|12.5
Awire|net@20|||900|pwr@0||-5.5|27.5|pmos@1|d|-5.5|25.5
Awire|net@21|||900|pwr@1||5|27.5|pmos@0|d|5|25.5
Awire|net@22|||0|pmos@0|g|2|23.5|pin@9||0.5|23.5
Awire|net@25|||0|pin@10||-2|21|pin@11||-5.5|21
Awire|net@51|||900|pmos@0|s|5|21.5|pin@21||5|21
Awire|net@52|||900|pmos@1|s|-5.5|21.5|pin@11||-5.5|21
Awire|net@53|||450|pin@9||0.5|23.5|pin@10||-2|21
Awire|net@55|||F3245|pin@22||1|21|pmos@1|g|-2.5|23.5
Awire|net@57|||2700|pin@27||5|19.5|pin@21||5|21
Awire|net@63|||0|pin@21||5|21|pin@22||1|21
Awire|net@64|||1800|M7|g|-8.5|15|M6|g|2|15
Awire|net@66|||2700|M7|d|-5.5|17|pin@24||-5.5|18.5
Awire|net@72|||900|pin@47||-5.5|20.5|pin@24||-5.5|18.5
Awire|net@73|||2700|M6|d|5|17|pin@27||5|19.5
Awire|net@81|||900|M7|s|-5.5|13|M1|d|-5.5|9.5
Awire|net@82|||2700|M2|d|5|9.5|M6|s|5|13
Awire|net@83|||0|pmos@2|d|6.5|25.5|pin@30||5|25.5
Awire|net@84|||2700|pin@30||5|25.5|pwr@1||5|27.5
Awire|net@85|||1800|pin@21||5|21|pin@31||6.5|21
Awire|net@86|||900|pmos@2|s|6.5|21.5|pin@31||6.5|21
Awire|net@88|||2700|pmos@3|d|-6.5|25.5|pin@33||-6.5|26
Awire|net@89|||1800|pin@33||-6.5|26|pin@34||-5.5|26
Awire|net@90|||2700|pin@34||-5.5|26|pwr@0||-5.5|27.5
Awire|net@91|||900|pmos@3|s|-6.5|21.5|pin@35||-6.5|21
Awire|net@92|||1800|pin@35||-6.5|21|pin@11||-5.5|21
Awire|net@93|||1800|pin@36||-9.5|15|M7|g|-8.5|15
Awire|net@94|||900|pmos@3|g|-9.5|23.5|pin@36||-9.5|15
Awire|net@95|||1800|pin@37||1|19.5|pin@27||5|19.5
Awire|net@96|||2700|pin@8||1|12.5|pin@37||1|19.5
Awire|net@97|||0|pin@38||-1.5|18.5|pin@24||-5.5|18.5
Awire|net@98|||2700|pin@6||-1.5|12.5|pin@38||-1.5|18.5
Awire|net@99|||1800|conn@0|y|-11|15|pin@36||-9.5|15
Awire|net@100|||1800|pmos@2|g|9.5|23.5|pin@32||10.5|23.5
Awire|net@101|||900|pin@32||10.5|23.5|pin@39||10.5|15
Awire|net@102|||0|pin@39||10.5|15|M6|g|2|15
Awire|net@105|||900|M9|s|-19|8.5|pin@40||-19|7.5
Awire|net@106|||0|pin@40||-19|7.5|pin@42||-20.5|7.5
Awire|net@107|||2700|pin@41||-21.5|7.5|M8|s|-21.5|8.5
Awire|net@108|||2700|gnd@2||-20.5|1.5|M10|s|-20.5|2
Awire|net@109|||0|pin@42||-20.5|7.5|pin@41||-21.5|7.5
Awire|net@110|||2700|M10|d|-20.5|6|pin@42||-20.5|7.5
Awire|net@111|||900|pwr@2||-25|6|pin@43||-25|4
Awire|net@112|||1800|pin@43||-25|4|M10|g|-23.5|4
Awire|net@113|||1800|conn@3|y|-25|10.5|M8|g|-24.5|10.5
Awire|net@114|||0|conn@4|y|-15|10.5|M9|g|-16|10.5
Awire|net@119|||900|pin@11||-5.5|21|pin@47||-5.5|20.5
Awire|net@120|||1800|pin@46||-21.5|20.5|pin@47||-5.5|20.5
Awire|net@121|||0|pin@37||1|19.5|pin@48||-19|19.5
Awire|net@122|||900|pin@48||-19|19.5|M9|d|-19|12.5
Awire|net@123|||2700|M8|d|-21.5|12.5|pin@46||-21.5|20.5
Awire|net@162|||2700|pin@72||5|18|pin@27||5|19.5
Awire|net@163|||0|M11|g|14|15|pin@39||10.5|15
Awire|net@164|||0|conn@2|a|19.5|18|pin@73||17.5|18
Awire|net@165|||0|pin@73||17.5|18|M11|s|16|18
Awire|net@166|||2700|cap@0|a|17.5|17|pin@73||17.5|18
Awire|net@167|||2700|gnd@3||17.5|11.5|cap@0|b|17.5|13
Awire|net@168|||0|M11|d|12|18|pin@72||5|18
Eclk||D5G2;X1.5;|conn@0|a|U
Einm||D5G2;|conn@4|a|U
Einp||D5G2;|conn@3|a|U
Eoutm|outp|D5G2;X-1;Y-2.5;|conn@2|y|U
X

# Cell diode_trr;1{sch}
Cdiode_trr;1{sch}||schematic|1233690386777|1233690389758|
Ngeneric:Facet-Center|art@0||0|0||||AV
NDiode|diode|D5G1;X-2.75;Y1;|1.75|11.5|||RR||SCHEM_diode(D5G1;Y-0.25;)S""
NGround|gnd@0||1.75|4.75||||
Ngeneric:Invisible-Pin|pin@0||-13.5|12.25|||||SIM_spice_card(D5G0.75;)S[Vgnd gnd 0 DC 0,Vin Vin 0 DC 0 PULSE 10 -10 10n 0.1n 0.1n 20n 40n,.model diode D is=1e-15 tt=10E-9 cj0=1e-12 vj=0.7 m=0.33,.tran 10p 25n,.options post]
NWire_Pin|pin@1||1.75|16.75||||
NWire_Pin|pin@2||-19.25|16.75||||
Ngeneric:Invisible-Pin|pin@3||-9.25|21.75|||||ART_message(D5G1;)SPlot Vin,VD and ID
NResistor|res@0||-9.25|16.75|||||SCHEM_resistance(D5G2;Y1.5;)S1k
Awire|D1|D5G1;X2.25;Y-3.25;||900|pin@1||1.75|16.75|diode|b|1.75|13.5
Awire|VD|D5G2;X2;Y1;||1800|res@0|b|-7.25|16.75|pin@1||1.75|16.75
Awire|Vin|D5G2;X-5.5;Y1;||0|res@0|a|-11.25|16.75|pin@2||-19.25|16.75
Awire|net@0|||2700|gnd@0||1.75|6.75|diode|a|1.75|9.5
X

# Cell example;1{lay}
Cexample;1{lay}||mocmos|1234900903413|1234902226385|
I10k;1{lay}|10k@0||52.5|0.5|||D5G4;
NMetal-2-Metal-3-Con|contact@2||-149.5|1||||
NMetal-1-Metal-2-Con|contact@3||-149.5|1|1|||
NMetal-1-Metal-2-Con|contact@4||233|1.5|1|||
NMetal-2-Metal-3-Con|contact@5||233|1.5||||
Ipad;1{lay}|pad@0||-149.5|274|||D5G4;
Ipad;1{lay}|pad@1||233|276.5|||D5G4;
AMetal-3|net@2|||S900|pad@0|I_O|-149.5|274|contact@2||-149.5|1
AMetal-1|net@3|||S0|10k@0|R|-20|1|contact@3||-149.5|1
AMetal-2|net@4|||S900|contact@2||-149.5|1|contact@3||-149.5|1
AMetal-1|net@5|||S1800|10k@0|L|125.5|1.5|contact@4||233|1.5
AMetal-3|net@6|||S900|pad@1|I_O|233|276.5|contact@5||233|1.5
AMetal-2|net@7|||S0|contact@4||233|1.5|contact@5||233|1.5
X

# Cell inv_20_10;1{ic}
Cinv_20_10;1{ic}||artwork|1239130022125|1239130064888|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NTriangle|art@2||4.5|0.5|6|6|RRR|
NCircle|art@3||8|0.5|1|1||
Nschematic:Bus_Pin|pin@0||0.5|0.5||||
Nschematic:Wire_Pin|pin@1||1.5|0.5||||
Nschematic:Bus_Pin|pin@2||9.5|0.5|||RR|
Nschematic:Wire_Pin|pin@3||8.5|0.5|||RR|
Ngeneric:Invisible-Pin|pin@8||3.75|0.5|||||ART_message(D5G1;)S20/10
Aschematic:wire|net@0|||0|pin@1||1.5|0.5|pin@0||0.5|0.5
Aschematic:wire|net@1|||1800|pin@3||8.5|0.5|pin@2||9.5|0.5
EA||D5G2;|pin@0||U
EAnot||D5G2;|pin@2||U
X

# Cell inv_20_10;1{lay}
Cinv_20_10;1{lay}||mocmos|1235074718781|1239131677897||DRC_last_good_drc_area_date()G1235075020612|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1235075020612
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-P-Active-Con|contact@0||-3.75|29.75||15||
NMetal-1-P-Active-Con|contact@1||7|29.75||15||
NMetal-1-N-Active-Con|contact@3||-3.75|1.5||5||
NMetal-1-N-Active-Con|contact@4||7.25|1.5||5||
NMetal-1-Polysilicon-1-Con|contact@5||-19|15||||
NN-Transistor|nmos@0||1.75|1.5|7||R||SIM_spice_model(D5G1;)SNMOS
NMetal-1-Pin|pin@0||7|4.5||||
NPolysilicon-1-Pin|pin@1||1.75|15||||
NMetal-1-Pin|pin@2||23|14||||
NMetal-1-Pin|pin@3||7|14||||
NP-Transistor|pmos@0||1.75|29.75|17||YRRR||SIM_spice_model(D5G1;)SPMOS
NMetal-1-P-Well-Con|q|D5G1;|-3.75|-13.5|5|||
NMetal-1-N-Well-Con|substr@0||-3|49.25|5|||
APolysilicon-1|net@0|||S2700|nmos@0|poly-right|1.75|8.5|pin@1||1.75|15
AP-Active|net@1|||S1800|contact@0||-3.75|29.75|pmos@0|diff-bottom|-2|29.75
AP-Active|net@2|||S0|contact@1||7|29.75|pmos@0|diff-top|5.5|29.75
AN-Active|net@3|||S1800|contact@3||-3.75|1.5|nmos@0|diff-top|-2|1.5
AN-Active|net@4|||S0|contact@4||7.25|1.5|nmos@0|diff-bottom|5.5|1.5
AMetal-1|net@5|||S900|pin@3||7|14|pin@0||7|4.5
AMetal-1|net@6|||S1800|pin@0||7|4.5|contact@4||7.25|4.5
AMetal-1|net@7|||S2700|q||-3.75|-13.5|contact@3||-3.75|-1.5
AMetal-1|net@8|||S900|substr@0||-3.75|49.25|contact@0||-3.75|37.75
APolysilicon-1|net@9|||S2700|pin@1||1.75|15|pmos@0|poly-left|1.75|17.75
APolysilicon-1|net@10|||S1800|contact@5||-19|15|pin@1||1.75|15
AMetal-1|net@11|||S900|contact@1||7|21.75|pin@3||7|14
AMetal-1|net@12|||S0|pin@2||23|14|pin@3||7|14
EA||D5G2;|contact@5||U
EAnot||D5G2;|pin@2||U
Egnd||D5G2;|q||U
Evdd||D5G2;|substr@0||U
X

# Cell inv_20_10;1{sch}
Cinv_20_10;1{sch}||schematic|1235074424391|1239130070226|
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||-4|5.5||||
NOff-Page|conn@1||6.5|5.5||||
NGround|gnd@0||3|-2.25|-1|-1.5||
Iinv_20_10;1{ic}|inv_20_1@0||7|11|||D5G4;
NTransistor|nmos@0||1|2|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NWire_Pin|pin@0||-1|8.5||||
NWire_Pin|pin@1||-1|2||||
NWire_Pin|pin@2||3|5.5||||
NWire_Pin|pin@3||-1|5.5||||
NTransistor|pmos@0||1|8.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||3|12.5|-1|-1||
Awire|net@0|||2700|gnd@0||3|-1|nmos@0|s|3|0
Awire|net@1|||900|pin@2||3|5.5|nmos@0|d|3|4
Awire|net@2|||900|pwr@0||3|12.5|pmos@0|d|3|10.5
Awire|net@3|||0|pmos@0|g|0|8.5|pin@0||-1|8.5
Awire|net@4|||900|pin@3||-1|5.5|pin@1||-1|2
Awire|net@5|||1800|pin@1||-1|2|nmos@0|g|0|2
Awire|net@6|||900|pmos@0|s|3|6.5|pin@2||3|5.5
Awire|net@7|||0|conn@1|a|4.5|5.5|pin@2||3|5.5
Awire|net@8|||900|pin@0||-1|8.5|pin@3||-1|5.5
Awire|net@9|||1800|conn@0|y|-2|5.5|pin@3||-1|5.5
EA||D5G1.5;X1;|conn@0|a|U
EAnot||D5G1.5;X-2.25;|conn@1|y|U
X

# Cell inv_200_100;1{ic}
Cinv_200_100;1{ic}||artwork|1235676637356|1235676742081|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NTriangle|art@2||0|1|6|6|RRR|
NCircle|art@3||3.5|1|1|1||
Nschematic:Bus_Pin|pin@0||-4|1||||
Nschematic:Wire_Pin|pin@1||-3|1||||
Nschematic:Bus_Pin|pin@2||5|1|||RR|
Nschematic:Wire_Pin|pin@3||4|1|||RR|
Ngeneric:Invisible-Pin|pin@4||-0.75|1|||||ART_message(D5G1;)S200/100
Aschematic:wire|net@0|||0|pin@1||-3|1|pin@0||-4|1
Aschematic:wire|net@1|||1800|pin@3||4|1|pin@2||5|1
EA||D5G2;|pin@0||U
EAi||D5G2;|pin@2||U
X

# Cell inv_200_100;1{lay}
Cinv_200_100;1{lay}||mocmos|1235677506936|1235679042538||DRC_last_good_drc_area_date()G1235679043516|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1235679043516
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-N-Active-Con|contact@0||-5.25|7.25||15||
NMetal-1-N-Active-Con|contact@1||4|7.25||15||
NMetal-1-N-Active-Con|contact@2||14|7.25||15||
NMetal-1-N-Active-Con|contact@3||35.5|7.25||15||
NMetal-1-N-Active-Con|contact@4||24.5|7.25||15||
NMetal-1-N-Active-Con|contact@5||46.25|7.25||15||
NMetal-1-Polysilicon-1-Con|contact@6||-16.5|20.5|7|||
NMetal-1-P-Active-Con|contact@14||3.5|61||35||
NMetal-1-P-Active-Con|contact@15||-8.5|61||35||
NMetal-1-P-Active-Con|contact@16||15.5|61||35||
NMetal-1-P-Active-Con|contact@18||27|61||35||
NMetal-1-P-Active-Con|contact@20||39|61||35||
NMetal-1-P-Active-Con|contact@21||50|61||35||
NN-Transistor|nmos@0||-1|7.25|17||R||SIM_spice_model(D5G1;)SNMOS
NN-Transistor|nmos@1||9|7.25|17||R||SIM_spice_model(D5G1;)SNMOS
NN-Transistor|nmos@2||19.5|7.25|17||R||SIM_spice_model(D5G1;)SNMOS
NN-Transistor|nmos@3||30|7.25|17||R||SIM_spice_model(D5G1;)SNMOS
NN-Transistor|nmos@4||40.5|7.25|17||R||SIM_spice_model(D5G1;)SNMOS
NMetal-1-Pin|pin@0||-4.75|-8.5||||
NMetal-1-Pin|pin@1||14|-8.5||||
NMetal-1-Pin|pin@2||4|23||||
NMetal-1-Pin|pin@3||24.5|23||||
NMetal-1-Pin|pin@4||35.5|-8.5||||
NMetal-1-Pin|pin@5||46.25|23||||
NPolysilicon-1-Pin|pin@6||-14|19.25||||
NPolysilicon-1-Pin|pin@7||40.5|39||||
NMetal-1-Pin|pin@8||-8.25|79||||
NPolysilicon-1-Pin|pin@9||33|19.25||||
NPolysilicon-1-Pin|pin@10||21|19.25||||
NPolysilicon-1-Pin|pin@11||9|39||||
NPolysilicon-1-Pin|pin@12||-2.5|19.25||||
NMetal-1-Pin|pin@13||3.5|23||||
NMetal-1-Pin|pin@15||27|23||||
NMetal-1-Pin|pin@16||50|23||||
NP-Transistor|pmos@0||-2.5|61|37||R||SIM_spice_model(D5G1;)SPMOS
NP-Transistor|pmos@1||9.5|61|37||R||SIM_spice_model(D5G1;)SPMOS
NP-Transistor|pmos@2||21|61|37||R||SIM_spice_model(D5G1;)SPMOS
NP-Transistor|pmos@3||33|61|37||R||SIM_spice_model(D5G1;)SPMOS
NP-Transistor|pmos@4||44|61|37||R||SIM_spice_model(D5G1;)SPMOS
NMetal-1-N-Well-Con|substr@0||18|92|51.5||XRR|
NMetal-1-P-Well-Con|well@0||22|-12|51.5|||
AN-Active|net@0|||S1800|contact@0||-5.75|7.25|nmos@0|diff-top|-4.75|7.25
AN-Active|net@1|||S1800|nmos@0|diff-bottom|2.75|6.75|contact@1||4.5|6.75
AN-Active|net@2|||S0|nmos@1|diff-top|5.25|7.5|contact@1||4|7.5
AN-Active|net@4|||S1800|nmos@1|diff-bottom|12.75|5.5|contact@2||14.5|5.5
AN-Active|net@5|||S0|nmos@2|diff-top|15.75|7.5|contact@2||14.5|7.5
AN-Active|net@6|||S1800|nmos@3|diff-bottom|33.75|5.5|contact@3||35.5|5.5
AN-Active|net@7|||S0|nmos@4|diff-top|36.75|8|contact@3||36|8
AN-Active|net@8|||S0|contact@4||24.5|7.25|nmos@2|diff-bottom|23.25|7.25
AN-Active|net@9|||S0|nmos@3|diff-top|26.25|3.5|contact@4||24.5|3.5
AN-Active|net@10|||S0|contact@5||46.25|6.5|nmos@4|diff-bottom|44.25|6.5
AMetal-1|net@11|||S900|contact@0||-4.75|7.25|pin@0||-4.75|-8.5
AMetal-1|net@12|||S1800|pin@0||-4.75|-8.5|pin@1||14|-8.5
AMetal-1|net@13|||S2700|pin@1||14|-8.5|contact@2||14|-0.75
AMetal-1|net@14|||S2700|contact@1||4|7.25|pin@2||4|23
AMetal-1|net@15|||S2700|contact@4||24.5|15.25|pin@3||24.5|23
AMetal-1|net@17|||S1800|pin@1||14|-8.5|pin@4||35.5|-8.5
AMetal-1|net@18|||S2700|pin@4||35.5|-8.5|contact@3||35.5|-0.75
AMetal-1|net@19|||S2700|contact@5||46.25|15.25|pin@5||46.25|23
AMetal-1|net@20|||S0|pin@5||46.25|23|pin@15||27|23
APolysilicon-1|net@21|||S0|nmos@4|poly-right|40.5|19.25|pin@9||33|19.25
APolysilicon-1|net@22|||S0|nmos@3|poly-right|30|19.25|nmos@2|poly-right|19.5|19.25
APolysilicon-1|net@23|||S0|nmos@2|poly-right|19.5|19.25|nmos@1|poly-right|9|19.25
APolysilicon-1|net@24|||S0|nmos@1|poly-right|9|19.25|nmos@0|poly-right|-1|19.25
APolysilicon-1|net@25|||S900|contact@6||-14|20|pin@6||-14|19.25
APolysilicon-1|net@26|||S1800|pin@6||-14|19.25|nmos@0|poly-right|-1|19.25
AP-Active|net@57|||S0|contact@14||3|76.5|pmos@0|diff-bottom|1.25|76.5
AP-Active|net@58|||S1800|contact@15||-9|59.5|pmos@0|diff-top|-6.25|59.5
AMetal-1|net@59|||S900|pin@4||35.5|-8.5|well@0||35.5|-12
AP-Active|net@60|||S0|contact@16||15|78|pmos@1|diff-bottom|13.25|78
AP-Active|net@62|||S0|pmos@1|diff-top|5.75|64|contact@14||3.5|64
AP-Active|net@63|||S0|contact@18||26.5|77|pmos@2|diff-bottom|24.75|77
AP-Active|net@65|||S0|contact@20||38.5|78.5|pmos@3|diff-bottom|36.75|78.5
AP-Active|net@66|||S0|pmos@3|diff-top|29.25|64|contact@18||27|64
AP-Active|net@67|||S0|pmos@2|diff-top|17.25|60.5|contact@16||15.5|60.5
AP-Active|net@68|||S0|pmos@4|diff-top|40.25|62.5|contact@20||39|62.5
AP-Active|net@69|||S0|contact@21||50|61|pmos@4|diff-bottom|47.75|61
APolysilicon-1|net@70|||S0|pmos@4|poly-left|44|39|pin@7||40.5|39
APolysilicon-1|net@71|||S900|pin@7||40.5|39|nmos@4|poly-right|40.5|19.25
AMetal-1|net@72|||S1800|contact@15||-8.5|79|pin@8||-8.25|79
AMetal-1|net@73|||S2700|pin@8||-8.25|79|substr@0||-8.25|92.5
AMetal-1|net@74|||S2700|contact@16||15.5|79|substr@0||15.5|92.5
AMetal-1|net@75|||S2700|contact@20||39|79|substr@0||39|92.5
APolysilicon-1|net@76|||S0|pin@9||33|19.25|nmos@3|poly-right|30|19.25
APolysilicon-1|net@77|||S900|pmos@3|poly-left|33|39|pin@9||33|19.25
APolysilicon-1|net@78|||S900|pmos@2|poly-left|21|39|pin@10||21|19.25
APolysilicon-1|net@79|||S0|pin@10||21|19.25|nmos@2|poly-right|19.5|19.25
APolysilicon-1|net@80|||S0|pmos@1|poly-left|9.5|39|pin@11||9|39
APolysilicon-1|net@81|||S900|pin@11||9|39|nmos@1|poly-right|9|19.25
APolysilicon-1|net@82|||S900|pmos@0|poly-left|-2.5|39|pin@12||-2.5|19.25
APolysilicon-1|net@83|||S1800|pin@12||-2.5|19.25|nmos@0|poly-right|-1|19.25
AMetal-1|net@84|||S900|contact@14||3.5|43|pin@13||3.5|23
AMetal-1|net@85|||S1800|pin@13||3.5|23|pin@2||4|23
AMetal-1|net@88|||S1800|pin@2||4|23|pin@3||24.5|23
AMetal-1|net@89|||S0|pin@15||27|23|pin@3||24.5|23
AMetal-1|net@90|||S900|contact@18||27|43|pin@15||27|23
AMetal-1|net@91|||S900|contact@21||50|43|pin@16||50|23
AMetal-1|net@92|||S0|pin@16||50|23|pin@5||46.25|23
EA||D5G2;|contact@6||U
EAi||D5G2;|pin@16||U
Egnd||D5G2;|well@0||U
Evdd||D5G2;|substr@0||U
X

# Cell inv_200_100;1{sch}
Cinv_200_100;1{sch}||schematic|1235676304307|1235679134839|
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||-1.5|7.25||||
NOff-Page|conn@1||8.5|7.25||||
NGround|gnd@0||4.25|-0.25||||
Iinv_200_100;1{ic}|inv_200_@0||13.25|13.75|||D5G4;
NTransistor|nmos@0||2.25|4.25|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D100.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NWire_Pin|pin@0||1.25|7.25||||
NWire_Pin|pin@1||4.25|7.25||||
NTransistor|pmos@0||2.25|10|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D200.0|SIM_spice_model(D5G0.5;RRRX-1.25;Y-1.5;)SPMOS
NPower|pwr@0||4.25|14.25||||
Awire|net@3|||900|pin@0||1.25|7.25|nmos@0|g|1.25|4.25
Awire|net@4|||900|pin@1||4.25|7.25|nmos@0|d|4.25|6.25
Awire|net@5|||2700|gnd@0||4.25|1.75|nmos@0|s|4.25|2.25
Awire|net@6|||900|pwr@0||4.25|14.25|pmos@0|d|4.25|12
Awire|net@7|||900|pmos@0|g|1.25|10|pin@0||1.25|7.25
Awire|net@8|||1800|conn@0|y|0.5|7.25|pin@0||1.25|7.25
Awire|net@9|||900|pmos@0|s|4.25|8|pin@1||4.25|7.25
Awire|net@10|||0|conn@1|a|6.5|7.25|pin@1||4.25|7.25
EA||D5G2;X1.25;|conn@0|a|U
EAi||D5G2;X-2.25;|conn@1|y|U
X

# Cell inv_ex;1{sch}
Cinv_ex;1{sch}||schematic|1239572726337|1239572841101|
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||7|1|-2|-2||
NTransistor|nmos@0||5|5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NWire_Pin|pin@0||0|5||||
NWire_Pin|pin@1||7|9.5||||
Ngeneric:Invisible-Pin|pin@2||14|7.5|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD VDD 0 DC 5,.op]
NWire_Pin|pin@3||7|16||||
NResistor|res@0||7|11.5|||R||SCHEM_resistance(D5G1;)S50k
Awire|VDD|D5G1;||0|nmos@0|g|4|5|pin@0||0|5
Awire|VDD|D5G1;||2700|res@0|b|7|13.5|pin@3||7|16
Awire|VDS|D5G1;||2700|nmos@0|d|7|7|pin@1||7|9.5
Awire|net@0|||2700|gnd@0||7|2|nmos@0|s|7|3
Awire|net@1|||900|res@0|a|7|9.5|pin@1||7|9.5
X

# Cell junk;1{sch}
Cjunk;1{sch}||schematic|1236107537629|1236107679681|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||-21.5|0.5|||||SCHEM_capacitance(D5G1;)S100M
NWire_Pin|pin@1||-18|-1.5||||
NWire_Pin|pin@2||-21.5|-5.5||||
NWire_Pin|pin@5||-21.5|-1.5||||
NResistor|res@0||-24|-5.5|||||SCHEM_resistance(D5G1;)S100
Awire|net@0|||1800|pin@5||-21.5|-1.5|pin@1||-18|-1.5
Awire|net@2|||0|pin@1||-18|-1.5|pin@1||-18|-1.5
Awire|net@3|||1800|res@0|b|-22|-5.5|pin@2||-21.5|-5.5
Awire|net@9|||900|pin@5||-21.5|-1.5|pin@2||-21.5|-5.5
Awire|net@10|||900|cap@0|b|-21.5|-1.5|pin@5||-21.5|-1.5
X

# Cell metaltest;1{lay}
Cmetaltest;1{lay}||mocmos|1233862102605|1233862852485||DRC_last_good_drc_area_date()G1233862519077|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1233862519077
NMetal-1-Metal-2-Con|contact@1||25|13||16||
NMetal-1-Metal-2-Con|contact@2||7|13|16|2||
NMetal-2-Metal-3-Con|contact@3||7|13||||
NMetal-1-Pin|pin@0||-27|13||||
NMetal-1-Pin|pin@1||27|13||||
NMetal-2-Pin|pin@3||-20|32||||
NMetal-2-Pin|pin@4||25|32||||
NMetal-2-Pin|pin@6||25|-5||||
NMetal-3-Pin|pin@9||-23|1||||
NMetal-3-Pin|pin@10||7|1||||
NMetal-3-Pin|pin@11||-23|22||||
NMetal-3-Node|plnode@0||-25|0|3|3||
AMetal-1|net@0||3|IJS1800|pin@0||-27|13|contact@2||7|13
AMetal-2|net@2|||S1800|pin@3||-20|32|pin@4||25|32
AMetal-2|net@7|||S900|pin@4||25|32|contact@1||25|13
AMetal-1|net@8||3|IJS1800|contact@1||25|13|pin@1||27|13
AMetal-2|net@9|||S900|contact@1||25|13|pin@6||25|-5
AMetal-3|net@11|||S1800|pin@9||-23|1|pin@10||7|1
AMetal-1|net@12||3|IJS1800|contact@2||7|13|contact@1||25|13
AMetal-3|net@13|||S2700|pin@10||7|1|contact@3||7|13
AMetal-2|net@14|||S900|contact@3||7|13|contact@2||7|13
AMetal-3|net@15||2|IJS2700|pin@9||-23|1|pin@11||-23|22
X

# Cell multi_example;2{sch}
Cmulti_example;2{sch}||schematic|1237487012238|1237487777814|
Ngeneric:Facet-Center|art@0||0|0||||AV
Iinv_200_100;1{ic}|inv[0:2]|D5G1;X1;Y3;|5|2|||D5G4;
NBus_Pin|pin@4||16|3||||
NWire_Pin|pin@5||-5.5|3||||
NWire_Pin|pin@8||13|-2.5||||
NBus_Pin|pin@9||13|3||||
Awire|in|D5G1;||0|inv[0:2]|A|1|3|pin@5||-5.5|3
Abus|n[1:2],n[0]|D5G1;||IJ1800|pin@9||13|3|pin@4||16|3
Awire|n[1]|D5G1;||2700|pin@8||13|-2.5|pin@9||13|3
Abus|net@2|||IJ1800|inv[0:2]|Ai|10|3|pin@9||13|3
X

# Cell multi_example;1{sch}
Cmulti_example;1{sch}||schematic|1237487012238|1237487482371|
Ngeneric:Facet-Center|art@0||0|0||||AV
Iinv_200_100;1{ic}|inv[0:2]|D5G1;X1;Y3;|5|2|||D5G4;
NBus_Pin|pin@3||-7|3||||
NBus_Pin|pin@4||16|3||||
Abus|n[0:2]|D5G1;||IJ0|inv[0:2]|A|1|3|pin@3||-7|3
Abus|n[1:2],n[0]|D5G1;||IJ1800|inv[0:2]|Ai|10|3|pin@4||16|3
X

# Cell op_amp_sim;2{sch}
Cop_amp_sim;2{sch}||schematic|1232654706515|1232655287958|
IAmp_gain_minus_one;1{ic}|Amp_gain@0||7|7|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||7|-4||||
Ngeneric:Invisible-Pin|pin@0||22|0|||||SIM_spice_card(D5G1;)S[.tran 1n 5u,Vgnd gnd 0 DC 0,Vin Vin 0 DC 0 sin 0 1 1MEG]
NWire_Pin|pin@1||-3|7||||
NWire_Pin|pin@2||19|7||||
Awire|Out|D5G1;||1800|Amp_gain@0|Out|12|7|pin@2||19|7
Awire|Vin|D5G1;||0|Amp_gain@0|In|2|7|pin@1||-3|7
Awire|net@2|||2700|gnd@0||7|-2|Amp_gain@0|gnd|7|-1
X

# Cell op_amp_sim;1{sch}
Cop_amp_sim;1{sch}||schematic|1232654706515|1232655399216|
IAmp_gain_minus_ten;1{ic}|Amp_gain@1||7|7|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||7|-4||||
Ngeneric:Invisible-Pin|pin@0||22|0|||||SIM_spice_card(D5G1;)S[.tran 1n 5u,Vgnd gnd 0 DC 0,Vin Vin 0 DC 0 sin 0 1 1MEG]
NWire_Pin|pin@1||-3|7||||
NWire_Pin|pin@2||19|7||||
Awire|Out|D5G1;||1800|Amp_gain@1|Out|12|7|pin@2||19|7
Awire|Vin|D5G1;||0|Amp_gain@1|In|2|7|pin@1||-3|7
Awire|net@2|||2700|gnd@0||7|-2|Amp_gain@1|gnd|7|-1
X

# Cell pad;1{lay}
Cpad;1{lay}||mocmos|1233864142269|1234902202282|
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-3-Pin|pin@2||0|0||||
NMetal-3-Node|q|D5G1;|0|0|250|250||
EI_O||D5G20;|pin@2||U
X

# Cell padframe;1{lay}
Cpadframe;1{lay}||mocmos|1233864034181|1233864805869|
Ipad;1{lay}|pad@4||-2093|-2130|||D5G4;
Ipad;1{lay}|pad@6||-1593|-2130|||D5G4;
Ipad;1{lay}|pad@8||-1093|-2130|||D5G4;
Ipad;1{lay}|pad@10||-593|-2130|||D5G4;
Ipad;1{lay}|pad@12||-93|-2130|||D5G4;
Ipad;1{lay}|pad@14||407|-2130|||D5G4;
Ipad;1{lay}|pad@16||907|-2130|||D5G4;
Ipad;1{lay}|pad@18||1407|-2130|||D5G4;
Ipad;1{lay}|pad@20||1907|-2130|||D5G4;
Ipad;1{lay}|pad@33||-2375|-2125|||D5G4;
Ipad;1{lay}|pad@52||2375|-2125|||D5G4;
Ipad;1{lay}|pad@63||-2375|-1875|||D5G4;
Ipad;1{lay}|pad@93||-2375|-1625|||D5G4;
Ipad;1{lay}|pad@112||2375|-1625|||D5G4;
Ipad;1{lay}|pad@123||-2375|-1375|||D5G4;
Ipad;1{lay}|pad@142||2375|-1375|||D5G4;
Ipad;1{lay}|pad@153||-2375|-1125|||D5G4;
Ipad;1{lay}|pad@172||2375|-1125|||D5G4;
Ipad;1{lay}|pad@183||-2375|-875|||D5G4;
Ipad;1{lay}|pad@202||2375|-875|||D5G4;
Ipad;1{lay}|pad@213||-2375|-625|||D5G4;
Ipad;1{lay}|pad@232||2375|-625|||D5G4;
Ipad;1{lay}|pad@243||-2375|-375|||D5G4;
Ipad;1{lay}|pad@262||2375|-375|||D5G4;
Ipad;1{lay}|pad@273||-2375|-125|||D5G4;
Ipad;1{lay}|pad@292||2375|-125|||D5G4;
Ipad;1{lay}|pad@303||-2375|125|||D5G4;
Ipad;1{lay}|pad@322||2375|125|||D5G4;
Ipad;1{lay}|pad@333||-2375|375|||D5G4;
Ipad;1{lay}|pad@352||2375|375|||D5G4;
Ipad;1{lay}|pad@363||-2375|625|||D5G4;
Ipad;1{lay}|pad@382||2375|625|||D5G4;
Ipad;1{lay}|pad@393||-2375|875|||D5G4;
Ipad;1{lay}|pad@412||2375|875|||D5G4;
Ipad;1{lay}|pad@423||-2375|1125|||D5G4;
Ipad;1{lay}|pad@442||2375|1125|||D5G4;
Ipad;1{lay}|pad@453||-2375|1375|||D5G4;
Ipad;1{lay}|pad@472||2375|1375|||D5G4;
Ipad;1{lay}|pad@483||-2375|1625|||D5G4;
Ipad;1{lay}|pad@502||2375|1625|||D5G4;
Ipad;1{lay}|pad@513||-2375|1875|||D5G4;
Ipad;1{lay}|pad@532||2375|1875|||D5G4;
Ipad;1{lay}|pad@543||-2375|2125|||D5G4;
Ipad;1{lay}|pad@562||2375|2125|||D5G4;
Ipad;1{lay}|pad@574||-2125|2375|||D5G4;
Ipad;1{lay}|pad@575||-1875|2375|||D5G4;
Ipad;1{lay}|pad@576||-1625|2375|||D5G4;
Ipad;1{lay}|pad@577||-1375|2375|||D5G4;
Ipad;1{lay}|pad@578||-1125|2375|||D5G4;
Ipad;1{lay}|pad@579||-875|2375|||D5G4;
Ipad;1{lay}|pad@580||-625|2375|||D5G4;
Ipad;1{lay}|pad@581||-375|2375|||D5G4;
Ipad;1{lay}|pad@582||-125|2375|||D5G4;
Ipad;1{lay}|pad@583||125|2375|||D5G4;
Ipad;1{lay}|pad@584||375|2375|||D5G4;
Ipad;1{lay}|pad@585||625|2375|||D5G4;
Ipad;1{lay}|pad@586||875|2375|||D5G4;
Ipad;1{lay}|pad@587||1125|2375|||D5G4;
Ipad;1{lay}|pad@588||1375|2375|||D5G4;
Ipad;1{lay}|pad@589||1625|2375|||D5G4;
Ipad;1{lay}|pad@590||1875|2375|||D5G4;
Ipad;1{lay}|pad@591||2125|2375|||D5G4;
X

# Cell ring_osc_31;1{ic}
Cring_osc_31;1{ic}||artwork|1239130548385|1239130640066|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Thicker-Polygon|art@1||0|1|6|4|||SCHEM_function(D5G1;Y1;)Sring_osc_31|trace()V[-3/-2,-3/2,3/2,3/-2,-3/-2]
Nschematic:Bus_Pin|pin@0||4|0|||RR|
Nschematic:Wire_Pin|pin@1||3|0|||RR|
Ngeneric:Invisible-Pin|pin@2||1|0|||||ART_message(D5G1;)Sosc_out
Aschematic:wire|net@0|||1800|pin@1||3|0|pin@0||4|0
Eout[30]||D5G1;X-1;|pin@0||U
X

# Cell ring_osc_31;1{lay}
Cring_osc_31;1{lay}||mocmos|1239131104062|1239131447039||DRC_last_good_drc_area_date()G1239131448748|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1239131448748
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-Metal-2-Con|contact@0||-17.5|16||||
NMetal-1-Metal-2-Con|contact@1||1423|16||||
Iinv_20_10;1{lay}|inv_20_1@0||8.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@1||54.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@2||100.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@3||146.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@4||192.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@5||238.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@6||284.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@7||330.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@8||376.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@9||422.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@10||468.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@11||514.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@12||560.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@13||606.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@14||652.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@15||698.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@16||744.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@17||790.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@18||836.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@19||882.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@20||928.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@21||974.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@22||1020.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@23||1066.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@24||1112.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@25||1158.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@26||1204.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@27||1250.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@28||1296.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@29||1342.5|1.5|||D5G4;
Iinv_20_10;1{lay}|inv_20_1@30||1388.5|1.5|||D5G4;
NMetal-1-Pin|pin@0||81|15.5||||
NMetal-1-Pin|pin@1||173|15.5||||
NMetal-1-Pin|pin@2||219|15.5||||
NMetal-1-Pin|pin@3||265|15.5||||
NMetal-1-Pin|pin@4||311|15.5||||
NMetal-1-Pin|pin@5||357|15.5||||
NMetal-1-Pin|pin@6||403|15.5||||
NMetal-1-Pin|pin@7||449|15.5||||
NMetal-1-Pin|pin@8||495|15.5||||
NMetal-1-Pin|pin@9||541|15.5||||
NMetal-1-Pin|pin@10||587|15.5||||
NMetal-1-Pin|pin@11||633|15.5||||
NMetal-1-Pin|pin@12||679|15.5||||
NMetal-1-Pin|pin@13||725|15.5||||
NMetal-1-Pin|pin@14||771|15.5||||
NMetal-1-Pin|pin@15||817|15.5||||
NMetal-1-Pin|pin@16||863|15.5||||
NMetal-1-Pin|pin@17||909|15.5||||
NMetal-1-Pin|pin@18||955|15.5||||
NMetal-1-Pin|pin@19||1001|15.5||||
NMetal-1-Pin|pin@20||1047|15.5||||
NMetal-1-Pin|pin@21||1093|15.5||||
NMetal-1-Pin|pin@22||1139|15.5||||
NMetal-1-Pin|pin@23||1185|15.5||||
NMetal-1-Pin|pin@24||1231|15.5||||
NMetal-1-Pin|pin@25||1277|15.5||||
NMetal-1-Pin|pin@26||1323|15.5||||
NMetal-1-Pin|pin@27||35|15.5||||
NMetal-1-Pin|pin@28||127|15.5||||
NMetal-1-Pin|pin@29||1369|15.5||||
NMetal-1-Pin|pin@30||1455|50.75||||
NMetal-2-Pin|pin@31||1457.5|16||||
NMetal-1-Pin|pin@32||1456|-12||||
AMetal-1|net@0|||S1800|inv_20_1@0|vdd|8.5|51|inv_20_1@1|vdd|48.5|51
AMetal-1|net@1|||S0|inv_20_1@3|vdd|140.5|50.75|inv_20_1@2|vdd|100.5|50.75
AMetal-1|net@2|||S0|inv_20_1@4|vdd|186.5|50.75|inv_20_1@3|vdd|146.5|50.75
AMetal-1|net@3|||S0|inv_20_1@5|vdd|232.5|50.75|inv_20_1@4|vdd|192.5|50.75
AMetal-1|net@4|||S0|inv_20_1@6|vdd|278.5|50.75|inv_20_1@5|vdd|238.5|50.75
AMetal-1|net@5|||S0|inv_20_1@7|vdd|324.5|50.75|inv_20_1@6|vdd|284.5|50.75
AMetal-1|net@6|||S0|inv_20_1@8|vdd|370.5|50.75|inv_20_1@7|vdd|330.5|50.75
AMetal-1|net@7|||S0|inv_20_1@9|vdd|416.5|50.75|inv_20_1@8|vdd|376.5|50.75
AMetal-1|net@8|||S0|inv_20_1@10|vdd|462.5|50.75|inv_20_1@9|vdd|422.5|50.75
AMetal-1|net@9|||S0|inv_20_1@11|vdd|508.5|50.75|inv_20_1@10|vdd|468.5|50.75
AMetal-1|net@10|||S0|inv_20_1@12|vdd|554.5|50.75|inv_20_1@11|vdd|514.5|50.75
AMetal-1|net@11|||S0|inv_20_1@13|vdd|600.5|50.75|inv_20_1@12|vdd|560.5|50.75
AMetal-1|net@12|||S0|inv_20_1@14|vdd|646.5|50.75|inv_20_1@13|vdd|606.5|50.75
AMetal-1|net@13|||S0|inv_20_1@15|vdd|692.5|50.75|inv_20_1@14|vdd|652.5|50.75
AMetal-1|net@14|||S0|inv_20_1@16|vdd|738.5|50.75|inv_20_1@15|vdd|698.5|50.75
AMetal-1|net@15|||S0|inv_20_1@17|vdd|784.5|50.75|inv_20_1@16|vdd|744.5|50.75
AMetal-1|net@16|||S0|inv_20_1@18|vdd|830.5|50.75|inv_20_1@17|vdd|790.5|50.75
AMetal-1|net@17|||S0|inv_20_1@19|vdd|876.5|50.75|inv_20_1@18|vdd|836.5|50.75
AMetal-1|net@18|||S0|inv_20_1@20|vdd|922.5|50.75|inv_20_1@19|vdd|882.5|50.75
AMetal-1|net@19|||S0|inv_20_1@21|vdd|968.5|50.75|inv_20_1@20|vdd|928.5|50.75
AMetal-1|net@20|||S0|inv_20_1@22|vdd|1014.5|50.75|inv_20_1@21|vdd|974.5|50.75
AMetal-1|net@21|||S0|inv_20_1@23|vdd|1060.5|50.75|inv_20_1@22|vdd|1020.5|50.75
AMetal-1|net@22|||S0|inv_20_1@24|vdd|1106.5|50.75|inv_20_1@23|vdd|1066.5|50.75
AMetal-1|net@23|||S0|inv_20_1@25|vdd|1152.5|50.75|inv_20_1@24|vdd|1112.5|50.75
AMetal-1|net@24|||S0|inv_20_1@26|vdd|1198.5|50.75|inv_20_1@25|vdd|1158.5|50.75
AMetal-1|net@25|||S0|inv_20_1@27|vdd|1244.5|50.75|inv_20_1@26|vdd|1204.5|50.75
AMetal-1|net@26|||S0|inv_20_1@28|vdd|1290.5|50.75|inv_20_1@27|vdd|1250.5|50.75
AMetal-1|net@27|||S0|inv_20_1@29|vdd|1336.5|50.75|inv_20_1@28|vdd|1296.5|50.75
AMetal-1|net@28|||S0|inv_20_1@30|vdd|1382.5|50.75|inv_20_1@29|vdd|1342.5|50.75
AMetal-1|net@29|||S0|inv_20_1@3|gnd|139.75|-12|inv_20_1@2|gnd|99.75|-12
AMetal-1|net@30|||S0|inv_20_1@4|gnd|185.75|-12|inv_20_1@3|gnd|145.75|-12
AMetal-1|net@31|||S0|inv_20_1@5|gnd|231.75|-12|inv_20_1@4|gnd|191.75|-12
AMetal-1|net@32|||S0|inv_20_1@6|gnd|277.75|-12|inv_20_1@5|gnd|237.75|-12
AMetal-1|net@33|||S0|inv_20_1@7|gnd|323.75|-12|inv_20_1@6|gnd|283.75|-12
AMetal-1|net@34|||S0|inv_20_1@8|gnd|369.75|-12|inv_20_1@7|gnd|329.75|-12
AMetal-1|net@35|||S0|inv_20_1@9|gnd|415.75|-12|inv_20_1@8|gnd|375.75|-12
AMetal-1|net@36|||S0|inv_20_1@10|gnd|461.75|-12|inv_20_1@9|gnd|421.75|-12
AMetal-1|net@37|||S0|inv_20_1@11|gnd|507.75|-12|inv_20_1@10|gnd|467.75|-12
AMetal-1|net@38|||S0|inv_20_1@12|gnd|553.75|-12|inv_20_1@11|gnd|513.75|-12
AMetal-1|net@39|||S0|inv_20_1@13|gnd|599.75|-12|inv_20_1@12|gnd|559.75|-12
AMetal-1|net@40|||S0|inv_20_1@14|gnd|645.75|-12|inv_20_1@13|gnd|605.75|-12
AMetal-1|net@41|||S0|inv_20_1@15|gnd|691.75|-12|inv_20_1@14|gnd|651.75|-12
AMetal-1|net@42|||S0|inv_20_1@16|gnd|737.75|-12|inv_20_1@15|gnd|697.75|-12
AMetal-1|net@43|||S0|inv_20_1@17|gnd|783.75|-12|inv_20_1@16|gnd|743.75|-12
AMetal-1|net@44|||S0|inv_20_1@18|gnd|829.75|-12|inv_20_1@17|gnd|789.75|-12
AMetal-1|net@45|||S0|inv_20_1@19|gnd|875.75|-12|inv_20_1@18|gnd|835.75|-12
AMetal-1|net@46|||S0|inv_20_1@20|gnd|921.75|-12|inv_20_1@19|gnd|881.75|-12
AMetal-1|net@47|||S0|inv_20_1@21|gnd|967.75|-12|inv_20_1@20|gnd|927.75|-12
AMetal-1|net@48|||S0|inv_20_1@22|gnd|1013.75|-12|inv_20_1@21|gnd|973.75|-12
AMetal-1|net@49|||S0|inv_20_1@23|gnd|1059.75|-12|inv_20_1@22|gnd|1019.75|-12
AMetal-1|net@50|||S0|inv_20_1@24|gnd|1105.75|-12|inv_20_1@23|gnd|1065.75|-12
AMetal-1|net@51|||S0|inv_20_1@25|gnd|1151.75|-12|inv_20_1@24|gnd|1111.75|-12
AMetal-1|net@52|||S0|inv_20_1@26|gnd|1197.75|-12|inv_20_1@25|gnd|1157.75|-12
AMetal-1|net@53|||S0|inv_20_1@27|gnd|1243.75|-12|inv_20_1@26|gnd|1203.75|-12
AMetal-1|net@54|||S0|inv_20_1@28|gnd|1289.75|-12|inv_20_1@27|gnd|1249.75|-12
AMetal-1|net@55|||S0|inv_20_1@29|gnd|1335.75|-12|inv_20_1@28|gnd|1295.75|-12
AMetal-1|net@56|||S0|inv_20_1@30|gnd|1381.75|-12|inv_20_1@29|gnd|1341.75|-12
AMetal-1|net@57|||S0|inv_20_1@1|gnd|47.75|-12|inv_20_1@0|gnd|7.75|-12
AMetal-1|net@58|||S0|inv_20_1@2|gnd|93.75|-12|inv_20_1@1|gnd|53.75|-12
AMetal-1|net@59|||S1800|inv_20_1@1|vdd|54.5|51|inv_20_1@2|vdd|94.5|51
AMetal-1|net@60|||S1800|inv_20_1@1|Anot|77.5|15.5|pin@0||81|15.5
AMetal-1|net@61|||S2700|pin@0||81|15.5|inv_20_1@2|A|81|16
AMetal-1|net@62|||S1800|inv_20_1@3|Anot|169.5|15.5|pin@1||173|15.5
AMetal-1|net@63|||S2700|pin@1||173|15.5|inv_20_1@4|A|173|16
AMetal-1|net@64|||S1800|inv_20_1@4|Anot|215.5|15.5|pin@2||219|15.5
AMetal-1|net@65|||S2700|pin@2||219|15.5|inv_20_1@5|A|219|16
AMetal-1|net@66|||S1800|inv_20_1@5|Anot|261.5|15.5|pin@3||265|15.5
AMetal-1|net@67|||S2700|pin@3||265|15.5|inv_20_1@6|A|265|16
AMetal-1|net@68|||S1800|inv_20_1@6|Anot|307.5|15.5|pin@4||311|15.5
AMetal-1|net@69|||S2700|pin@4||311|15.5|inv_20_1@7|A|311|16
AMetal-1|net@70|||S1800|inv_20_1@7|Anot|353.5|15.5|pin@5||357|15.5
AMetal-1|net@71|||S2700|pin@5||357|15.5|inv_20_1@8|A|357|16
AMetal-1|net@72|||S1800|inv_20_1@8|Anot|399.5|15.5|pin@6||403|15.5
AMetal-1|net@73|||S2700|pin@6||403|15.5|inv_20_1@9|A|403|16
AMetal-1|net@74|||S1800|inv_20_1@9|Anot|445.5|15.5|pin@7||449|15.5
AMetal-1|net@75|||S2700|pin@7||449|15.5|inv_20_1@10|A|449|16
AMetal-1|net@76|||S1800|inv_20_1@10|Anot|491.5|15.5|pin@8||495|15.5
AMetal-1|net@77|||S2700|pin@8||495|15.5|inv_20_1@11|A|495|16
AMetal-1|net@78|||S1800|inv_20_1@11|Anot|537.5|15.5|pin@9||541|15.5
AMetal-1|net@79|||S2700|pin@9||541|15.5|inv_20_1@12|A|541|16
AMetal-1|net@80|||S1800|inv_20_1@12|Anot|583.5|15.5|pin@10||587|15.5
AMetal-1|net@81|||S2700|pin@10||587|15.5|inv_20_1@13|A|587|16
AMetal-1|net@82|||S1800|inv_20_1@13|Anot|629.5|15.5|pin@11||633|15.5
AMetal-1|net@83|||S2700|pin@11||633|15.5|inv_20_1@14|A|633|16
AMetal-1|net@84|||S1800|inv_20_1@14|Anot|675.5|15.5|pin@12||679|15.5
AMetal-1|net@85|||S2700|pin@12||679|15.5|inv_20_1@15|A|679|16
AMetal-1|net@86|||S1800|inv_20_1@15|Anot|721.5|15.5|pin@13||725|15.5
AMetal-1|net@87|||S2700|pin@13||725|15.5|inv_20_1@16|A|725|16
AMetal-1|net@88|||S1800|inv_20_1@16|Anot|767.5|15.5|pin@14||771|15.5
AMetal-1|net@89|||S2700|pin@14||771|15.5|inv_20_1@17|A|771|16
AMetal-1|net@90|||S1800|inv_20_1@17|Anot|813.5|15.5|pin@15||817|15.5
AMetal-1|net@91|||S2700|pin@15||817|15.5|inv_20_1@18|A|817|16
AMetal-1|net@92|||S1800|inv_20_1@18|Anot|859.5|15.5|pin@16||863|15.5
AMetal-1|net@93|||S2700|pin@16||863|15.5|inv_20_1@19|A|863|16
AMetal-1|net@94|||S1800|inv_20_1@19|Anot|905.5|15.5|pin@17||909|15.5
AMetal-1|net@95|||S2700|pin@17||909|15.5|inv_20_1@20|A|909|16
AMetal-1|net@96|||S1800|inv_20_1@20|Anot|951.5|15.5|pin@18||955|15.5
AMetal-1|net@97|||S2700|pin@18||955|15.5|inv_20_1@21|A|955|16
AMetal-1|net@98|||S1800|inv_20_1@21|Anot|997.5|15.5|pin@19||1001|15.5
AMetal-1|net@99|||S2700|pin@19||1001|15.5|inv_20_1@22|A|1001|16
AMetal-1|net@100|||S1800|inv_20_1@22|Anot|1043.5|15.5|pin@20||1047|15.5
AMetal-1|net@101|||S2700|pin@20||1047|15.5|inv_20_1@23|A|1047|16
AMetal-1|net@102|||S1800|inv_20_1@23|Anot|1089.5|15.5|pin@21||1093|15.5
AMetal-1|net@103|||S2700|pin@21||1093|15.5|inv_20_1@24|A|1093|16
AMetal-1|net@104|||S1800|inv_20_1@24|Anot|1135.5|15.5|pin@22||1139|15.5
AMetal-1|net@105|||S2700|pin@22||1139|15.5|inv_20_1@25|A|1139|16
AMetal-1|net@106|||S1800|inv_20_1@25|Anot|1181.5|15.5|pin@23||1185|15.5
AMetal-1|net@107|||S2700|pin@23||1185|15.5|inv_20_1@26|A|1185|16
AMetal-1|net@108|||S1800|inv_20_1@26|Anot|1227.5|15.5|pin@24||1231|15.5
AMetal-1|net@109|||S2700|pin@24||1231|15.5|inv_20_1@27|A|1231|16
AMetal-1|net@110|||S1800|inv_20_1@27|Anot|1273.5|15.5|pin@25||1277|15.5
AMetal-1|net@111|||S2700|pin@25||1277|15.5|inv_20_1@28|A|1277|16
AMetal-1|net@112|||S1800|inv_20_1@28|Anot|1319.5|15.5|pin@26||1323|15.5
AMetal-1|net@113|||S2700|pin@26||1323|15.5|inv_20_1@29|A|1323|16
AMetal-1|net@114|||S1800|inv_20_1@0|Anot|31.5|15.5|pin@27||35|15.5
AMetal-1|net@115|||S2700|pin@27||35|15.5|inv_20_1@1|A|35|16
AMetal-1|net@116|||S1800|inv_20_1@2|Anot|123.5|15.5|pin@28||127|15.5
AMetal-1|net@117|||S2700|pin@28||127|15.5|inv_20_1@3|A|127|16
AMetal-1|net@118|||S1800|inv_20_1@29|Anot|1365.5|15.5|pin@29||1369|15.5
AMetal-1|net@119|||S2700|pin@29||1369|15.5|inv_20_1@30|A|1369|16
AMetal-1|net@121|||S0|inv_20_1@0|A|-11|16.5|contact@0||-17.5|16.5
AMetal-1|net@122|||S0|contact@1||1423|15.5|inv_20_1@30|Anot|1411.5|15.5
AMetal-2|net@124|||S1800|contact@0||-17.5|16|contact@1||1423|16
AMetal-1|net@125|||S1800|inv_20_1@30|vdd|1385.5|50.75|pin@30||1455|50.75
AMetal-2|net@126|||S1800|contact@1||1423|16|pin@31||1457.5|16
AMetal-1|net@127|||S1800|inv_20_1@30|gnd|1384.75|-12|pin@32||1456|-12
Egnd||D5G2;|pin@32||U
Eout[30]||D5G2;|pin@31||U
Evdd||D5G2;|pin@30||U
X

# Cell ring_osc_31;1{sch}
Cring_osc_31;1{sch}||schematic|1239129979516|1239130548386|
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||26|2.5||||
Iinv_20_10;1{ic}|inv[0:30]|D5G1;X1;Y3;|5|2|||D5G4;
NBus_Pin|pin@4||21|2.5||||
NBus_Pin|pin@5||-3|2.5||||
Iring_osc_31;1{ic}|ring_osc@0||32.5|10.5|||D5G4;
Awire|net@0|||0|conn@0|a|24|2.5|pin@4||21|2.5
Abus|out[0:30]|D5G1;||IJ1800|inv[0:30]|Anot|14.5|2.5|pin@4||21|2.5
Abus|out[30],out[0:29]|D5G1;||IJ0|inv[0:30]|A|5.5|2.5|pin@5||-3|2.5
Eout[30]||D5G1.5;X-1.5;|conn@0|y|U
X

# Cell sim_inv_dc;1{sch}
Csim_inv_dc;1{sch}||schematic|1239302578164|1239303507660|
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||17|-1.75|-1|-1.5||
NGround|gnd@1||10.5|-1.75|-1|-1.5||
NTransistor|nmos@0||15|2.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
NTransistor|nmos@1||8.5|2.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SNMOS
Ngeneric:Invisible-Pin|pin@0||0.5|0.5|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vgnd gnd 0 DC 0,vin vin 0 DC 0,.dc vin 0 5 1m]
NWire_Pin|pin@1||-2.5|6||||
NWire_Pin|pin@2||21|6||||
NWire_Pin|pin@5||13|9||||
NWire_Pin|pin@6||13|2.5||||
NWire_Pin|pin@9||6.5|9||||
NWire_Pin|pin@10||6.5|2.5||||
NWire_Pin|pin@11||6.5|6||||
NWire_Pin|pin@12||17|6||||
NWire_Pin|pin@13||13|6||||
NWire_Pin|pin@14||10.5|6||||
NTransistor|pmos@0||15|9|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NTransistor|pmos@1||8.5|9|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SPMOS
NPower|pwr@0||17|13|-1|-1||
NPower|pwr@1||10.5|13|-1|-1||
Awire|Vin|D5G1;||1800|pin@1||-2.5|6|pin@11||6.5|6
Awire|Vout|D5G1;||0|pin@2||21|6|pin@12||17|6
Awire|net@2|||2700|gnd@0||17|-0.5|nmos@0|s|17|0.5
Awire|net@4|||900|pwr@0||17|13|pmos@0|d|17|11
Awire|net@5|||0|pmos@0|g|14|9|pin@5||13|9
Awire|net@7|||1800|pin@6||13|2.5|nmos@0|g|14|2.5
Awire|net@12|||2700|nmos@0|d|17|4.5|pin@12||17|6
Awire|net@13|||2700|pin@6||13|2.5|pin@13||13|6
Awire|net@14|||2700|nmos@1|d|10.5|4.5|pin@14||10.5|6
Awire|net@15|||2700|pin@10||6.5|2.5|pin@11||6.5|6
Awire|net@16|||2700|gnd@1||10.5|-0.5|nmos@1|s|10.5|0.5
Awire|net@17|||900|pwr@1||10.5|13|pmos@1|d|10.5|11
Awire|net@18|||0|pmos@1|g|7.5|9|pin@9||6.5|9
Awire|net@19|||1800|pin@10||6.5|2.5|nmos@1|g|7.5|2.5
Awire|net@20|||2700|pin@11||6.5|6|pin@9||6.5|9
Awire|net@23|||2700|pin@12||17|6|pmos@0|s|17|7
Awire|net@25|||2700|pin@13||13|6|pin@5||13|9
Awire|net@26|||2700|pin@14||10.5|6|pmos@1|s|10.5|7
Awire|net@27|||0|pin@13||13|6|pin@14||10.5|6
X

# Cell sim_ring_osc_31;1{lay}
Csim_ring_osc_31;1{lay}||mocmos|1239131524759|1239131574929||DRC_last_good_drc_area_date()G1239131580354|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1239131580354
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-Pin|pin@0||1374|47.75||||
NMetal-2-Pin|pin@1||1371.5|13||||
NMetal-1-Pin|pin@2||1368.5|-15||||
Ngeneric:Invisible-Pin|pin@3||1278|145|||||SIM_spice_card(D5G20;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vgnd gnd 0 DC 0,.ic v(osc_out)=5,.tran 10p 60n UIC]
Iring_osc_31;1{lay}|ring_osc@0||-109.5|-3|||D5G4;
AMetal-1|gnd|D5G1;||S1800|ring_osc@0|gnd|1346.5|-15|pin@2||1368.5|-15
AMetal-2|osc_out|D5G1;||S1800|ring_osc@0|out[30]|1348|13|pin@1||1371.5|13
AMetal-1|vdd|D5G1;||S1800|ring_osc@0|vdd|1345.5|47.75|pin@0||1374|47.75
X

# Cell sim_ring_osc_31;1{sch}
Csim_ring_osc_31;1{sch}||schematic|1239130690535|1239130960831|
Ngeneric:Facet-Center|art@0||0|0||||AV
NWire_Pin|pin@0||14|3||||
Ngeneric:Invisible-Pin|pin@1||10.5|9.5|||||SIM_spice_card(D5G1;)S[.include C5_models.txt,VDD vdd 0 DC 5,Vgnd gnd 0 DC 0,.ic v(osc_out)=5,.tran 10p 60n UIC]
Iring_osc_31;1{ic}|ring_osc@0||5.5|3|||D5G4;
Awire|osc_out|D5G1;X0.5;Y1;||1800|ring_osc@0|out[30]|9.5|3|pin@0||14|3
X

# Cell vdiv;1{sch}
Cvdiv;1{sch}||schematic|1232480685009|1236107627105|
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||8|-2||||
NWire_Pin|pin@0||8|6||||
Ngeneric:Invisible-Pin|pin@2||1|2|||||SIM_spice_card(D5G1;)S[Vin Vin 0 DC 1,Vgnd gnd 0 DC 0,.op]
NWire_Pin|pin@3||-2|6||||
NResistor|res@0||3|6|||||SCHEM_resistance(D5G1;Y1;)S1k
NResistor|res@1||8|3|||R||SCHEM_resistance(D5G1;Y1;)S1k
Awire|Vin|D5G1;Y1;||0|res@0|a|1|6|pin@3||-2|6
Awire|Vout|D5G1;Y1;||0|pin@0||8|6|res@0|b|5|6
Awire|net@0|||2700|gnd@0||8|0|res@1|a|8|1
Awire|net@1|||2700|res@1|b|8|5|pin@0||8|6
X

# Cell vdiv3to1;1{lay}
Cvdiv3to1;1{lay}||mocmos|1233085972512|1236107627125||DRC_last_good_drc_area_date()G1233086014509
I10k;1{lay}|10k@0||10|20|||D5G4;
I10k;1{lay}|10k@1||10|-7|||D5G4;
I10k;1{lay}|10k@2||11|-31|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-2-Metal-3-Con|contact@0||-85|20|10|||
NMetal-1-Metal-2-Con|contact@1||-85|20|1|||
Ngeneric:Invisible-Pin|pin@6||-11|42|||||SIM_spice_card(D5G4;)S[Vin Vin 0 DC 1,Vgnd gnd 0 DC 0,.tran 0 1]
NMetal-1-Pin|pin@8||83.5|-46.5||||
NMetal-3-Pin|pin@9||-85|57.5||||
AMetal-1|net@7|||S900|10k@0|L|83|20|10k@1|L|83|-6
AMetal-1|net@8|||S900|10k@1|R|-61.5|-7.5|10k@2|R|-61.5|-30.5
AMetal-1|net@9|||S900|10k@2|L|83.5|-30.5|pin@8||83.5|-46.5
AMetal-3|net@10|||S900|pin@9||-85|57.5|contact@0||-85|20
AMetal-2|net@12|||S900|contact@0||-85|20|contact@1||-85|20
AMetal-1|net@13|||S0|10k@0|R|-62|20|contact@1||-85|20
X

# Cell vdiv3to1;1{sch}
Cvdiv3to1;1{sch}||schematic|1233086340942|1233086572711|
I10k;1{sch}|10k@0||0|6|||D5G4;
I10k;1{sch}|10k@1||16|-12|R||D5G4;
I10k;1{sch}|10k@2||16|-16|RRR||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
Ngeneric:Invisible-Pin|pin@0||-1|17|||||SIM_spice_card(D5G1;)S[Vin Vin 0 DC 1,Vgnd gnd 0 DC 0,.tran 0 1]
NWire_Pin|pin@1||16|6||||
NWire_Pin|pin@3||-11|6||||
NWire_Pin|pin@4||0|-28||||
Awire|1_3|D5G1;||900|10k@1|L|16|-12|10k@2|L|16|-16
Awire|2_3|D5G1;||900|pin@1||16|6|10k@1|R|16|0
Awire|gnd|D5G1;||0|10k@2|R|16|-28|pin@4||0|-28
Awire|net@0|||1800|10k@0|R|12|6|pin@1||16|6
Awire|vin|D5G2;||0|10k@0|L|0|6|pin@3||-11|6
X

# Cell welcome;1{lay}
Cwelcome;1{lay}||mocmos|1225555651218|1225555767593|
Ngeneric:Facet-Center|art@0||0|0||||AV
Ngeneric:Invisible-Pin|pin@0||0|0|||||ART_message(D5G4;)S[Welcome to ECE 5/410,Spring 2009]
X