Homework assignments and Project Information for ECE 510/410 Physical IC Design, Spring 2009
Homework guidelines are found here.
All layouts and schematics should be drawn using Electric.
Simulations should be performed using LTspice.
Drawing schematics using LTspice will result in zero credit.
Note that an A in front of
the problem indicates an additional
problem from the book’s webpage,
not a problem from the book’s end-of-chapter problems.
HW10 – due
Thursday, May 7, A13.1, A13.2, and A13.3
HW9 – due
Thursday, April 9, A10.1, A10.4, A10.5, A10.7, A10.8, A10.9, A11.1, and A11.2
HW8 – due
Thursday, March 19, A6.2, A6.3, A6.4, A6.7, A6.8, A6.11, A6.16, A6.17, also
email me, per the instructions below, a NAND gate jelib using 10/2 PMOS and
NMOS devices.
HW7 – due
Tuesday, March 3, A5.2, A5.4, A5.8, A5.9, A5.10, also, email me before lecture
starts, a clean jelib containing schematics, icons, and layout for inverters
with sizes of 20/10, 100/50, and 500/250 (all minimum length devices) that NCC,
DRC, and ERC correctly. Note that there should only be 3 cell groups in your
jelib since it’s clean. Your grade on this jelib will be directly based on the
aesthetics of your cells and the use of metal to connect power, ground, and
output to the cells (especially for the larger inverter).
HW6 – due
Tuesday, February 24, problems A4.1-A4.6, for the A4.6 solution email, before
lecture starts on 2/24, a clean jelib (nothing in the jelib except the cells
related to problem A4.6) to jbaker at boisestate.edu.
HW5 – due
Tuesday, February 17, problems: A1.21-A1.23, A2.6-A2.7, A2.16-A2.17, A3.1-A3.3,
A3.7
HW4 – due
Thursday, February 5, Problems: A2.14 and A2.15
HW3 – due
Tuesday, February 3, Problems: A2.11-A.2.13
HW2 – due
Thursday, January 29, Problems: A1.18-A1.20
HW1 – due Tuesday, January 27, Problems: A1.12-A1.17
Course projects – Due Tuesday, May
5. Read the policy on the course
webpage concerning turning in late work. These projects are NOT group efforts.
What you turn in should be your own work. Your project reports, a PDF
containing no more than 20 pages, should detail:
o
The reasons for
the topology you selected
o
Design
considerations
o
Hand calculations
with comparisons to simulations (with and without parasitics)
o
A pin diagram for
the layout (how to connect the layout to bond pads if we fabricate the design)
o
Clear layout
documentation (zoomed in and outlines of the layout for easy grading).
o
Layout should be
as “tight” as possible.
o
I should be able
to figure out what to simulate and how to simulate it without any effort (make
sure this is very clear!)
o
I will have the
MOSFET models in C:\Electric\C5_models.txt
o
I’ll perform an
NCC and a DRC on what you send (so make sure everything is clean before
emailing me!)
·
I should receive the electronic report
(PDF) and jelib via email (jbaker at boisestate.edu)
prior to the beginning of class (12:10 PM) on Tuesday May 5, 2009.
Project – Design a 6-bit Flash analog-to-digital converter
(ADC). The icon for your schematic design should be pin-for-pin compatible with
the ideal 6-bit ADC in ECE5410_project.jelib
so that your design can be tested in the simulations seen in this jelib. Note
that you can use the schematic (icon) of the ideal DAC to help with the
simulations of your layout too (for ease of viewing the 6-bit digital data
coming out of your ADC).
For graduate students in ECE
510 design the 6-bit DAC too. Simulate the ADC you designed with the ideal DAC,
the DAC you designed with the ideal ADC, and the DAC/ADC you designed together.