Homework assignments and Project Information for ECE 510/410 Physical IC Design, Spring 2010
Homework guidelines are found here.
All layouts and schematics should be drawn using Electric.
Simulations should be performed using LTspice.
Drawing schematics using LTspice will result in zero credit.
Note that an A in front of
the problem indicates an additional
problem from the book’s webpage,
not a problem from the book’s end-of-chapter problems.
HW12 – due
Monday, April 12, (use the C5 process for all HW problems) A11.6, A11.10,
A11.11, and using 20/2 PMOS and 10/2 NMOS make a concise schematic of a
31-stage ring oscillator and its corresponding layout (need additional help?
see here).
Simulate both the layout and the schematic (and compare oscillation frequency
to hand calculations in the HW solutions) then email me the jelib before class
starts on April 12). Call the cell _ring_osc. I will save your jelib to
my desktop and simulate your layout and schematic. On my desktop and in
C:\Electric I will have the C5 models.
HW11 – due
Monday, April 5, (use the C5 process for all HW problems) A10.1-A10.4, and
A11.1-A11.2
HW10 – due
Wednesday, March 24, A6.9, A6.13-A6.15, A6.19, A6.20, and layout, draw the
schematic and icon, for the circuit seen in Fig. 13.22 (an edge-triggered
D-Flip-Flop). The icon should look like a D-Flip-Flop. Use an added inverter
inside the DFF to generate the complement of the input clock (to generate clock
bar). The icon should look like a DFF. Note the off-page nodes should be (only)
clock, Q, Q_bar, and D. Simulate
the operation of your DFF (both layout and schematic). Use
10/2 PMOS and NMOS devices.
HW9 – due
Monday, March 15, A6.1-A6.5
HW8 – due Monday, March 8, Create, using Electric, a NAND gate schematic,
layout, and icon using 20/2 NMOS and PMOS devices. Make sure your NAND gate NCCs, DRCs, and
Well Checks without errors.
HW7 – due
Wednesday, February 24, A5.1, A5.2, and A5.4
HW6 – due
Monday, February 22, layout, and sketch the cross-sectional views, of the
resistors seen in Table 4.1 (use L = 10*W with W being minimum allowed by the
design rules), repeat example 4.2 if the width of the wire is increased to 10,
describe how a “field device” is formed when poly1 is present over FOX (use
pictures to augment your description).
HW5 – due
Wednesday, February 17, A4.2-A4.5, Also create an inverter (layout, schematic,
icon) using a 20/2 NMOS and a 40/2 PMOS. Hand sketch cross-sectional views
across the NMOS device, PMOS device, n-well connections, and p-well (substrate)
connections to illustrate your vast understanding.
HW4 – due
Wednesday, February 10, problems A3.8-A3.9, A4.1
HW3 – due
Monday, February 8, problems A3.1-A3.5, also lay out
the 40 pin padframe for a MOSIS chip in the C5 process discussed in Tutorial_6.
Ensure your layout NCCs, DRCs, Well Checks without errors.
HW2 – due
Monday, February 1, problems A1.10, A1.11, A2.1, A2.6-A2.8, A2.13
HW1 – due Monday, January 25, problems A1.1, A1.3-A1.5
Course projects –
Due Monday,
May 3. These projects are NOT group efforts (if you turn in
identical layouts/schematics you will get an F in the course). What you turn in
should be your own work. I should receive the electronic report (PDF, at most 20 pages in length
following the HW guidelines linked above) and jelib via email (jbaker at boisestate.edu) prior to the
beginning of class (6:45 PM) on Monday May 3, 2009.
Project –
Design, lay out, and simulate a 6-bit Flash
analog-to-digital converter (ADC, see Fig. 29.21) using the dynamic comparator
seen in Fig. 25.35. The icon for your schematic design should be pin-for-pin
compatible with the ideal 6-bit ADC in ece5410_project.jelib so that your design can be tested in
the simulations seen in this jelib. Note that you can use the schematic (icon) of
the ideal DAC to help with the simulations of your layout too (for ease of
viewing the 6-bit digital data coming out of your ADC).
·
Design considerations
o Selecting the lengths of the inverter to trade-off power for speed (make this clear with simulations and discussions)
o The design of the thermometer decoder to reduce/eliminate sparkle in the output code
o Why you may need to use TGs instead of pass-gates (PGs) in the dynamic comparator
·
Hand calculations with comparisons to
simulations (with and without parasitics)
·
A pin diagram for the layout (how to connect the
layout to bond pads if we fabricate the design)
·
Clear layout documentation (zoomed in and
outlines of the layout for easy grading).
·
Layout should be as “tight” as possible.
·
I should be able to figure out what to simulate
and how to simulate it without any effort (make sure this is very clear!)
·
I will have the MOSFET models in
C:\Electric\C5_models.txt
·
I’ll perform an NCC and a DRC on what you send
(so make sure everything is clean before emailing me!)
· Ensure unused cells are not present in the jelib you send me
For graduate students in ECE 510 also design, lay out, and simulate the 6-bit DAC. Use the R-2R topology seen in Fig. 30.14 here and the poly2 resistors with hi-res block available in the C5 process. Simulate the ADC you designed with the ideal DAC, the DAC you designed with the ideal ADC, and the DAC/ADC you designed together. Notice that there is no load capacitance requirement for the DAC. Here is help on the thermometer to binary decoder.