Homework assignments for ECE 5/411 CMOS Analog IC Design, Fall 2007
Homework guidelines are found here.
HW#1 – due Wednesday September 5, problems A9.3, A9.4, A9.5, A9.23, and A9.24
HW#2 – due Monday, September 10, problems A9.6, A9.7, and A9.9
HW#3 – due Wednesday, September 12, problem A9.13
HW#4 – due Monday, September 17, problems A9.12, A9.15, A9.20
HW#5 – due Monday, September 24, problems A9.18, A20.1, A20.2, A20.6, A20.7, A20.8, A20.12
HW#6 – due Monday, October 1, problems A20.10, A20.11, A20.14, A20.16, A20.17, A20.22, A20.25
HW#7 – due Monday, October 8, problems A20.28, A20.29, A21.1, A21.3, A21.5, A21.6, A21.9
HW#8 – due Monday, October 22, problems A21.13, A21.14, A21.18, and A21.19
HW#9 – due Monday, October 29, problems A1.4 (yes, chapter 1), A21.20, A21.21, A21.22, A21.23
HW#10 – due Wednesday, November 7, problems A21.24, A21.28, A21.29, A21.30, A22.1, A22.2, A22.4, A22.5,
HW#11 – due Monday, December 17, problems A23.4, A23.5, A23.9, A24.3, A24.6
Test#1 – Wednesday, October 10
Test#2 – Monday, November 12
Final exam – Monday, December 17 from 8:15 to 10:15 pm
Project Due December 10 at 5 pm before lecture starts via email (no late work accepted!) –
Design a 10-bit R-2R DAC using TSMC’s 180 nm (CM018) process and a VDD of 1.8 V. The
report should be 10 pages or less, typed, in PDF format (no title page). Since the length of
the report is short, you should put considerable thought into the information you put into it.
No text smaller than 10 point should be used and I should be able read your graphs without
a magnifying glass ;-)
The DAC should use 1k polysilcon resistors so the delay through the resistors is negligible.
You are told this because in a real design the delay through the resistors is a big factor
as you increase the resistor’s size. Large resistors lower power but slow down the performance.
Note that the process selected for this project, TSMC’s CM018 process, is a single poly process.
You should model your compensation capacitor appropriately with parasitics (this should be
in your report, how you modeled it and why).
Use the 1.8-V VDD for the reference voltage. The DAC’s LSB is 1.8V/2^10 or 1.76 mV. When
the input of the DAC is 11 1111 1111 the output should be close to 1.8V while an input of
00 0000 0000 should give an output close to 0 V. Note that your op-amp’s output won’t
swing all the way to the power supply rails so there will be nonlinearity.
Your grade will be based on the performance of your design in the LTspice simulation tests
seen in ECE5411_project.zip and the report. Note the name of your design should be “mydac”.
I will rank performance (settling time, linearity, power, etc.) and assign grades accordingly
(this isn’t a team project and you should only work on your own project).
Email both the PDF report and a zipped up directory of your DAC using your name, e.g.,
“yourname.zip”. I will unzip the contents of your zip into the folder in ECE5411_project.zip
above. Since you’ve named your DAC the name I asked you to all I have to do is open the test
simulations and hit the run button. Life is good!