Homework assignments and Project Information for ECE 5/411 CMOS Analog IC Design, Fall 2008
Homework guidelines are found here.
HW#10 – due Tuesday, December 9, problem A24.6
HW#9 – due Tuesday, November 4, problems A23.3, A23.4, A23.5, A23.7, A23.9
HW#8 – due Tuesday, October 28, problems A22.4, A22.6, A22.7, A22.9, A22.13
HW#7 – due Tuesday, October 21, problems A21.22, A21.23, A21.25, A22.1, and A22.3
HW#6 – due Tuesday, October 14, problems A21.9, A21.12, A21.14, A21.16, and A21.19
HW#5 – due Tuesday, October 7, problems A21.1, A21.2, A21.3, and A21.4
HW#4 – due Tuesday, September 23, problems A20.1, A20.2, A20.5, A20.6, and A20.8
HW#3 – due Tuesday, September 16, problems A9.9, A9.14, A9.19, and A9.20
HW#2 – due Tuesday, September 9, problems A9.11 - A9.13
HW#1 – due Tuesday, September 2, problems A9.1, A9.2, A9.3, and A9.4
Course project - using On Semiconductor's 500 nm process (C5 with two polysilicon layers and 3 levels of metal with a lambda of 300 nm) design an op-amp that can operate with a VDD down to 2 V while driving 10 pF (max) and 1k (min) load. The MOSIS information for this process is located here and the SPICE models are C5_models.txt
Other requirements are:
· DC open-loop gain > 80 dB under all load and VDD conditions
· Gain-bandwidth product should be > 1 MHz
· CMRR > 90 dB at 100 kHz
· PSRR > 90 dB at 100 kHz
· Slew-rate with maximum load > 1V/microsecond
Your report should detail your design considerations, simulation schematics with results, and provide a table summarizing the results (input CMR as a function of VDD, unity gain frequency, power, slew-rate, etc.) This is not a team effort. A significant portion of your grade will be based on your report. I will grade these reports with you present (you will need to come to my office where we’ll go through your design, simulations, and report).
Your report is due at the beginning of class on Thursday, Dec. 4. You can bring your SPICE files with you when we meet.