# header information:
Hece5418_f08|8.10

# Views:
Vicon|ic
Vlayout|lay
Vschematic|sch

# Technologies:
Tmocmos|ScaleFORmocmos()D25.0|mocmosAnalog()BT|mocmosNumberOfMetalLayers()I3

# Cell Array_8_by_8;1{lay}
CArray_8_by_8;1{lay}||mocmos|1220488390741|1220488838831||DRC_last_good_drc_area_date()G1220488455401|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1220488455401
Ngeneric:Facet-Center|art@0||0|0||||AV
Imbit;1{lay}|mbit@4||5.75|11.25|||D5G4;
Imbit;1{lay}|mbit@5||27.75|11.25|||D5G4;
Imbit;1{lay}|mbit@6||49.75|11.25|||D5G4;
Imbit;1{lay}|mbit@7||71.75|11.25|||D5G4;
Imbit;1{lay}|mbit@8||93.75|11.25|||D5G4;
Imbit;1{lay}|mbit@9||115.75|11.25|||D5G4;
Imbit;1{lay}|mbit@10||137.75|11.25|||D5G4;
Imbit;1{lay}|mbit@11||159.75|11.25|||D5G4;
Imbit;1{lay}|mbit@12||5.75|47.75|||D5G4;
Imbit;1{lay}|mbit@13||27.75|47.75|||D5G4;
Imbit;1{lay}|mbit@14||49.75|47.75|||D5G4;
Imbit;1{lay}|mbit@15||71.75|47.75|||D5G4;
Imbit;1{lay}|mbit@16||93.75|47.75|||D5G4;
Imbit;1{lay}|mbit@17||115.75|47.75|||D5G4;
Imbit;1{lay}|mbit@18||137.75|47.75|||D5G4;
Imbit;1{lay}|mbit@19||159.75|47.75|||D5G4;
Imbit;1{lay}|mbit@20||5.75|84.25|||D5G4;
Imbit;1{lay}|mbit@21||27.75|84.25|||D5G4;
Imbit;1{lay}|mbit@22||49.75|84.25|||D5G4;
Imbit;1{lay}|mbit@23||71.75|84.25|||D5G4;
Imbit;1{lay}|mbit@24||93.75|84.25|||D5G4;
Imbit;1{lay}|mbit@25||115.75|84.25|||D5G4;
Imbit;1{lay}|mbit@26||137.75|84.25|||D5G4;
Imbit;1{lay}|mbit@27||159.75|84.25|||D5G4;
Imbit;1{lay}|mbit@28||5.75|120.75|||D5G4;
Imbit;1{lay}|mbit@29||27.75|120.75|||D5G4;
Imbit;1{lay}|mbit@30||49.75|120.75|||D5G4;
Imbit;1{lay}|mbit@31||71.75|120.75|||D5G4;
Imbit;1{lay}|mbit@32||93.75|120.75|||D5G4;
Imbit;1{lay}|mbit@33||115.75|120.75|||D5G4;
Imbit;1{lay}|mbit@34||137.75|120.75|||D5G4;
Imbit;1{lay}|mbit@35||159.75|120.75|||D5G4;
Imbit;1{lay}|mbit@36||5.75|157.25|||D5G4;
Imbit;1{lay}|mbit@37||27.75|157.25|||D5G4;
Imbit;1{lay}|mbit@38||49.75|157.25|||D5G4;
Imbit;1{lay}|mbit@39||71.75|157.25|||D5G4;
Imbit;1{lay}|mbit@40||93.75|157.25|||D5G4;
Imbit;1{lay}|mbit@41||115.75|157.25|||D5G4;
Imbit;1{lay}|mbit@42||137.75|157.25|||D5G4;
Imbit;1{lay}|mbit@43||159.75|157.25|||D5G4;
Imbit;1{lay}|mbit@44||5.75|193.75|||D5G4;
Imbit;1{lay}|mbit@45||27.75|193.75|||D5G4;
Imbit;1{lay}|mbit@46||49.75|193.75|||D5G4;
Imbit;1{lay}|mbit@47||71.75|193.75|||D5G4;
Imbit;1{lay}|mbit@48||93.75|193.75|||D5G4;
Imbit;1{lay}|mbit@49||115.75|193.75|||D5G4;
Imbit;1{lay}|mbit@50||137.75|193.75|||D5G4;
Imbit;1{lay}|mbit@51||159.75|193.75|||D5G4;
Imbit;1{lay}|mbit@52||5.75|230.25|||D5G4;
Imbit;1{lay}|mbit@53||27.75|230.25|||D5G4;
Imbit;1{lay}|mbit@54||49.75|230.25|||D5G4;
Imbit;1{lay}|mbit@55||71.75|230.25|||D5G4;
Imbit;1{lay}|mbit@56||93.75|230.25|||D5G4;
Imbit;1{lay}|mbit@57||115.75|230.25|||D5G4;
Imbit;1{lay}|mbit@58||137.75|230.25|||D5G4;
Imbit;1{lay}|mbit@59||159.75|230.25|||D5G4;
Imbit;1{lay}|mbit@60||5.75|266.75|||D5G4;
Imbit;1{lay}|mbit@61||27.75|266.75|||D5G4;
Imbit;1{lay}|mbit@62||49.75|266.75|||D5G4;
Imbit;1{lay}|mbit@63||71.75|266.75|||D5G4;
Imbit;1{lay}|mbit@64||93.75|266.75|||D5G4;
Imbit;1{lay}|mbit@65||115.75|266.75|||D5G4;
Imbit;1{lay}|mbit@66||137.75|266.75|||D5G4;
Imbit;1{lay}|mbit@67||159.75|266.75|||D5G4;
NMetal-1-Pin|pin@0||-33.25|40.5||||
NP-Well-Node|plnode@1||87|145.25|200|300||A
NMetal-1-N-Well-Con|substr@0||88.75|-1|195|||
NMetal-1-P-Well-Con|well@0||-8|40.5||||
APolysilicon-1|net@6||8|S0|mbit@11|vdd|159|21.5|mbit@10|vdd|137|21.5
APolysilicon-1|net@7||8|S0|mbit@10|vdd|137|21.5|mbit@9|vdd|115|21.5
APolysilicon-1|net@8||8|S0|mbit@9|vdd|115|21.5|mbit@8|vdd|93|21.5
APolysilicon-1|net@9||8|S0|mbit@8|vdd|93|21.5|mbit@7|vdd|71|21.5
APolysilicon-1|net@10||8|S0|mbit@7|vdd|71|21.5|mbit@6|vdd|49|21.5
APolysilicon-1|net@11||8|S0|mbit@6|vdd|49|21.5|mbit@5|vdd|27|21.5
APolysilicon-1|net@12||8|S0|mbit@5|vdd|27|21.5|mbit@4|vdd|5|21.5
AMetal-1|net@13|||S900|mbit@60|bl|11|263.5|mbit@52|bl|11|228
AMetal-1|net@14|||S900|mbit@52|bl|9.25|227|mbit@44|bl|9.25|191.5
AMetal-1|net@15|||S900|mbit@44|bl|13.5|190.5|mbit@36|bl|13.5|155
AMetal-1|net@16|||S900|mbit@36|bl|13.5|154|mbit@28|bl|13.5|118.5
AMetal-1|net@17|||S900|mbit@28|bl|11|117.5|mbit@20|bl|11|82
AMetal-1|net@18|||S900|mbit@20|bl|12.75|81|mbit@12|bl|12.75|45.5
AMetal-1|net@19|||S900|mbit@12|bl|11.75|44.5|mbit@4|bl|11.75|9
AMetal-1|net@20|||S0|well@0||-8|40.5|pin@0||-33.25|40.5
Egnd||D5G2;|well@0||G
X

# Cell Array_8_by_8;1{sch}
CArray_8_by_8;1{sch}||schematic|1220033843404|1220921784315|
Ngeneric:Facet-Center|art@0||0|0||||AV
Imbit;1{sch}|mbit@0||-0.5|-1.25|||D5G4;
Imbit;1{sch}|mbit@1||14.5|-1.25|||D5G4;
Imbit;1{sch}|mbit@2||-0.5|-14|||D5G4;
Imbit;1{sch}|mbit@3||14.5|-14|||D5G4;
NWire_Pin|pin@0||0.5|11.5||||
NWire_Pin|pin@1||15.5|11||||
NWire_Pin|pin@2||0.5|-1.25||||
NWire_Pin|pin@3||15.5|-1.75||||
NWire_Pin|pin@4||-5.75|-7.25||||
NWire_Pin|pin@5||-5|5.5||||
Awire|net@0|||0|mbit@1|wl|18|3.5|mbit@0|wl|3|3.5
Awire|net@1|||1800|mbit@0|vdd|7|5.5|mbit@1|vdd|22|5.5
Awire|net@2|||2700|mbit@0|bit|0.5|0.25|pin@0||0.5|11.5
Awire|net@3|||2700|mbit@1|bit|15.5|0.25|pin@1||15.5|11
Awire|net@4|||0|mbit@3|wl|18|-9.25|mbit@2|wl|3|-9.25
Awire|net@5|||1800|mbit@2|vdd|7|-7.25|mbit@3|vdd|22|-7.25
Awire|net@6|||2700|mbit@2|bit|0.5|-12.5|pin@2||0.5|-1.25
Awire|net@7|||2700|mbit@3|bit|15.5|-12.5|pin@3||15.5|-1.75
Awire|net@8|||2700|pin@2||0.5|-1.25|mbit@0|bit|0.5|0.25
Awire|net@9|||2700|pin@3||15.5|-1.75|mbit@1|bit|15.5|0.25
Awire|net@10|||0|mbit@2|vdd|7|-7.25|pin@4||-5.75|-7.25
Awire|net@11|||0|mbit@0|vdd|7|5.5|pin@5||-5|5.5
X

# Cell NAND;1{ic}
CNAND;1{ic}||artwork|1181686811906|1181761654468|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NCircle|art@1||4.25|1.25|1|1||
NCircle|art@2||0.75|1.25|6|6|RRR||ART_degrees()F[0.0,3.1415927]
NOpened-Polygon|art@3||-0.25|1.25|2|6|||trace()V[1/-3,-1/-3,-1/3,1/3]
Nschematic:Bus_Pin|pin@0||-3.25|2.5||||
Nschematic:Wire_Pin|pin@1||-1.25|2.5||||
Nschematic:Bus_Pin|pin@2||-3.25|0.25||||
Nschematic:Wire_Pin|pin@3||-1.25|0.25||||
Nschematic:Bus_Pin|pin@4||5|1.25||||
Ngeneric:Universal-Pin|pin@10||6.75|1.25|-1|-1||
Nschematic:Wire_Pin|pin@11||4.75|1.25||||
Ngeneric:Invisible-Pin|pin@12||1|1.5|||||ART_message(D5G1;)SNAND
Aschematic:wire|net@0|||0|pin@1||-1.25|2.5|pin@0||-3.25|2.5
Aschematic:wire|net@1|||0|pin@3||-1.25|0.25|pin@2||-3.25|0.25
Aschematic:wire|net@5|||1800|pin@11||4.75|1.25|pin@10||6.75|1.25
EA||D5G2;|pin@0||U
EB||D5G2;|pin@2||U
EOut||D5G2;X2.5;Y0.25;|pin@4||U
X

# Cell NAND;2{sch}
CNAND;2{sch}||schematic|1181686687953|1208961066281|
NTransistor|M2|D5G1;X1;Y-3;|-16|13.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G1;X-1;Y-3.25;)SP_50n
NTransistor|M3|D5G1;X1;Y-3;|-9.25|13.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G1;X-1;Y-3.25;)SP_50n
NTransistor|M4|D5G1;X1.5;Y-3.25;|-9.25|5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X-1.25;Y-2.75;)SN_50n
NTransistor|M5|D5G1;X1.5;Y-3.25;|-9.25|0|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X-1.25;Y-2.75;)SN_50n
INAND;1{ic}|NAND@0||3.25|15.75|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@1||-7.25|-5.75||||
NWire_Pin|pin@0||-11.75|5||||
NWire_Pin|pin@1||-17|0||||
NWire_Pin|pin@2||-25|0||||
NWire_Pin|pin@3||-7.25|16.75||||
NWire_Pin|pin@4||-14|16.75||||
NWire_Pin|pin@5||-7.25|10.25||||
NWire_Pin|pin@6||-14|10.25||||
NWire_Pin|pin@10||-11.75|13.25||||
NWire_Pin|pin@11||-24.75|5||||
NWire_Pin|pin@12||-2|10.25||||
NPower|pwr@0||-14|19||||
Awire|net@0|||2700|M4|d|-7.25|7|pin@5||-7.25|10.25
Awire|net@1|||1800|pin@4||-14|16.75|pin@3||-7.25|16.75
Awire|net@2|||900|pin@3||-7.25|16.75|M3|d|-7.25|15.25
Awire|net@3|||2700|M2|d|-14|15.25|pin@4||-14|16.75
Awire|net@4|||2700|pin@5||-7.25|10.25|M3|s|-7.25|11.25
Awire|net@5|||1800|pin@6||-14|10.25|pin@5||-7.25|10.25
Awire|net@6|||900|M2|s|-14|11.25|pin@6||-14|10.25
Awire|net@9|||0|M3|g|-10.25|13.25|pin@10||-11.75|13.25
Awire|net@10|||2700|gnd@1||-7.25|-3.75|M5|s|-7.25|-2
Awire|net@11|||1800|pin@2||-25|0|pin@1||-17|0
Awire|net@14|||900|pin@10||-11.75|13.25|pin@0||-11.75|5
Awire|net@16|||900|M2|g|-17|13.25|pin@1||-17|0
Awire|net@17|||2700|pin@4||-14|16.75|pwr@0||-14|19
Awire|net@19|||0|M4|g|-10.25|5|pin@0||-11.75|5
Awire|net@20|||2700|M5|d|-7.25|2|M4|s|-7.25|3
Awire|net@21|||1800|pin@1||-17|0|M5|g|-10.25|0
Awire|net@23|||1800|pin@5||-7.25|10.25|pin@12||-2|10.25
Awire|net@24|||0|pin@0||-11.75|5|pin@11||-24.75|5
EA||D5G2;X-0.75;|pin@11||U
EB||D5G2;X-0.75;|pin@2||U
EOut||D5G2;X2;Y0.25;|pin@12||U
X

# Cell NAND;1{sch}
CNAND;1{sch}||schematic|1181686687953|1208961066281|
NTransistor|M2|D5G1;X1;Y-3;|-16|13.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G1;X-1;Y-3.25;)SP_50n
NTransistor|M3|D5G1;X1;Y-3;|-9.25|13.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G1;X-1;Y-3.25;)SP_50n
NTransistor|M4|D5G1;X1.5;Y-3.25;|-9.25|5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X-1.25;Y-2.75;)SN_50n
NTransistor|M5|D5G1;X1.5;Y-3.25;|-9.25|0|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X-1.25;Y-2.75;)SN_50n
INAND;1{ic}|NAND@0||3.25|15.75|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@1||-7.25|-5.75||||
NWire_Pin|pin@0||-11.75|5||||
NWire_Pin|pin@1||-17|0||||
NWire_Pin|pin@2||-25|0||||
NWire_Pin|pin@3||-7.25|16.75||||
NWire_Pin|pin@4||-14|16.75||||
NWire_Pin|pin@5||-7.25|10.25||||
NWire_Pin|pin@6||-14|10.25||||
NWire_Pin|pin@10||-11.75|13.25||||
NWire_Pin|pin@11||-24.75|5||||
NWire_Pin|pin@12||-2|10.25||||
NPower|pwr@0||-14|19||||
Awire|net@0|||2700|M4|d|-7.25|7|pin@5||-7.25|10.25
Awire|net@1|||1800|pin@4||-14|16.75|pin@3||-7.25|16.75
Awire|net@2|||900|pin@3||-7.25|16.75|M3|d|-7.25|15.25
Awire|net@3|||2700|M2|d|-14|15.25|pin@4||-14|16.75
Awire|net@4|||2700|pin@5||-7.25|10.25|M3|s|-7.25|11.25
Awire|net@5|||1800|pin@6||-14|10.25|pin@5||-7.25|10.25
Awire|net@6|||900|M2|s|-14|11.25|pin@6||-14|10.25
Awire|net@9|||0|M3|g|-10.25|13.25|pin@10||-11.75|13.25
Awire|net@10|||2700|gnd@1||-7.25|-3.75|M5|s|-7.25|-2
Awire|net@11|||1800|pin@2||-25|0|pin@1||-17|0
Awire|net@14|||900|pin@10||-11.75|13.25|pin@0||-11.75|5
Awire|net@16|||900|M2|g|-17|13.25|pin@1||-17|0
Awire|net@17|||2700|pin@4||-14|16.75|pwr@0||-14|19
Awire|net@19|||0|M4|g|-10.25|5|pin@0||-11.75|5
Awire|net@20|||2700|M5|d|-7.25|2|M4|s|-7.25|3
Awire|net@21|||1800|pin@1||-17|0|M5|g|-10.25|0
Awire|net@23|||1800|pin@5||-7.25|10.25|pin@12||-2|10.25
Awire|net@24|||0|pin@0||-11.75|5|pin@11||-24.75|5
EA||D5G2;X-0.75;|pin@11||U
EB||D5G2;X-0.75;|pin@2||U
EOut||D5G2;X2;Y0.25;|pin@12||U
X

# Cell Rn;1{lay}
CRn;1{lay}||mocmos|1219712847772|1219713504358||DRC_last_good_drc_area_date()G1219713506348|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1219713506348
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-N-Active-Con|contact@0||1.75|-4.5|5|||
NN-Transistor|nmos@0||1.75|1.75|7||||SIM_spice_model(D5G1;)SN_50n
NPolysilicon-1-Pin|pin@0||-15|1.75||||
NN-Active-Pin|pin@1||1.75|13.5||||
Ngeneric:Invisible-Pin|pin@2||-24.25|13|||||SIM_spice_card(D5G1;)S[.ic v(vout)=1,Cl Vout 0 1p,vin Vin 0 pulse 0 1 5n 100p,.include cmosedu_models.txt,.tran 100p 20n UIC]
NMetal-1-P-Well-Con|well@0||1.75|-13.5|5|||
APolysilicon-1|Vin|D5G1;||S0|nmos@0|poly-left|-5.25|1.75|pin@0||-15|1.75|ATTR_R(D5G1;N)D30.225
AN-Active|Vout|D5G1;||S2700|nmos@0|diff-top|1.75|5.5|pin@1||1.75|13.5
AN-Active|net@1|||S900|nmos@0|diff-bottom|1.75|-2|contact@0||1.75|-5
AMetal-1|net@2||7|IJS900|contact@0||1.75|-4.5|well@0||1.75|-13.75
Egnd||D5G2;|well@0||G
X

# Cell Rn;1{sch}
CRn;1{sch}||schematic|1219711616188|1219713133130|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||9.75|3.25|||||SCHEM_capacitance(D5G1;)S1p
NGround|gnd@1||9.75|-2||||
NGround|gnd@2||3|-3||||
NTransistor|nmos@0||1|2|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.75;)SN_50n
NWire_Pin|pin@0||3|6.75||||
NWire_Pin|pin@1||9.75|6.75||||
NWire_Pin|pin@2||-4.25|2||||
Ngeneric:Invisible-Pin|pin@3||-4.25|7.5|||||SIM_spice_card(D5G1;)S[.ic v(vout)=1,vin Vin 0 pulse 0 1 5n 100p,.include cmosedu_models.txt,.tran 100p 20n UIC]
Awire|Vin|D5G1;||0|nmos@0|g|0|2|pin@2||-4.25|2
Awire|Vout|D5G1;||1800|pin@0||3|6.75|pin@1||9.75|6.75
Awire|net@1|||2700|nmos@0|d|3|4|pin@0||3|6.75
Awire|net@3|||900|pin@1||9.75|6.75|cap@0|a|9.75|5.25
Awire|net@4|||900|cap@0|b|9.75|1.25|gnd@1||9.75|0
Awire|net@7|||2700|gnd@2||3|-1|nmos@0|s|3|0
X

# Cell Rp;1{sch}
CRp;1{sch}||schematic|1219712450088|1219712670382|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||3|-2.75|||||SCHEM_capacitance(D5G1;)S1p
NGround|gnd@0||3|-7.5||||
NWire_Pin|pin@0||-5|2.25||||
Ngeneric:Invisible-Pin|pin@1||-7|7.5|||||SIM_spice_card(D5G1;)S[.ic v(vout)=0,VDD VDD 0 DC 1,vin Vin 0 pulse 1 0 5n 100p,.include cmosedu_models.txt,.tran 100p 20n UIC]
NTransistor|pmos@0||1|2.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.5;)SP_50n
NPower|pwr@0||3|8.5||||
Awire|Vin|D5G1;||0|pmos@0|g|0|2.25|pin@0||-5|2.25
Awire|Vout|D5G1;||2700|cap@0|a|3|-0.75|pmos@0|s|3|0.25
Awire|net@0|||900|pwr@0||3|8.5|pmos@0|d|3|4.25
Awire|net@3|||2700|gnd@0||3|-5.5|cap@0|b|3|-4.75
X

# Cell array_jake;1{lay}
Carray_jake;1{lay}||mocmos|1220923477915|1220924202619||DRC_last_good_drc_area_date()G1220924212776|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1220924212776
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-Metal-2-Con|contact@0||45.5|-18||||
NMetal-1-Metal-2-Con|contact@1||16|-18||||
NMetal-1-Polysilicon-1-Con|contact@2||-20.5|123.25||||
NMetal-1-Polysilicon-1-Con|contact@3||-21.5|85.75||||
NMetal-1-Polysilicon-1-Con|contact@4||-21.75|48.75||||
NMetal-1-Polysilicon-1-Con|contact@5||-20.25|12||||
Imbit_jake;1{lay}|mbit_jak@0||0.5|0.5|||D5G4;
Imbit_jake;1{lay}|mbit_jak@1||30|0.5|||D5G4;
Imbit_jake;1{lay}|mbit_jak@2||0.5|37.75|||D5G4;
Imbit_jake;1{lay}|mbit_jak@3||30|37.75|||D5G4;
Imbit_jake;1{lay}|mbit_jak@4||0.5|75|||D5G4;
Imbit_jake;1{lay}|mbit_jak@5||30|75|||D5G4;
Imbit_jake;1{lay}|mbit_jak@6||0.5|112.25|||D5G4;
Imbit_jake;1{lay}|mbit_jak@7||30|112.25|||D5G4;
NMetal-1-Pin|pin@0||2|-17.75||||
NMetal-1-Pin|pin@1||31.5|-18||||
NMetal-2-Pin|pin@4||39|-18||||
NMetal-2-Pin|pin@5||21|-18||||
NMetal-2-Pin|pin@6||21|-18||||
NMetal-2-Pin|pin@7||-13.5|-18||||
NMetal-2-Pin|pin@8||16|-18||||
NPolysilicon-1-Pin|pin@9||-14.25|1.5||||
NPolysilicon-1-Pin|pin@10||-15.25|38.75||||
NPolysilicon-1-Pin|pin@11||-15.75|76||||
NPolysilicon-1-Pin|pin@12||-15|113.25||||
NPolysilicon-1-Pin|pin@14||-15.75|48.75||||
NPolysilicon-1-Pin|pin@16||-17|86||||
NPolysilicon-1-Pin|pin@17||-15.75|123.25||||
NPolysilicon-1-Pin|pin@18||-15.75|123.25||||
NPolysilicon-1-Pin|pin@19||-17|86||||
NPolysilicon-1-Pin|pin@20||-15.75|48.75||||
NPolysilicon-1-Pin|pin@22||-20.5|12||||
NMetal-1-Pin|pin@24||-21.75|12||||
NMetal-1-Pin|pin@25||-21.75|86.25||||
NMetal-1-Pin|pin@26||-21.5|123.75||||
NMetal-1-Pin|pin@27||-26.25|11.75||||
NMetal-1-Pin|pin@28||-20.25|11.75||||
AMetal-1|net@0|||S900|mbit_jak@6|bit|1.5|108|mbit_jak@4|bit|1.5|71.75
AMetal-1|net@1|||S900|mbit_jak@4|bit|2.5|70.75|mbit_jak@2|bit|2.5|34.5
AMetal-1|net@2|||S900|mbit_jak@2|bit|1.5|33.5|mbit_jak@0|bit|1.5|-3
AMetal-1|net@3|||S900|mbit_jak@0|bit|2|-3.25|pin@0||2|-17.75
AMetal-1|net@4|||S900|mbit_jak@7|bit|31|108|mbit_jak@5|bit|31|71.75
AMetal-1|net@5|||S900|mbit_jak@5|bit|31.5|70.75|mbit_jak@3|bit|31.5|34.5
AMetal-1|net@6|||S900|mbit_jak@3|bit|29.75|33.5|mbit_jak@1|bit|29.75|-2.75
AMetal-1|net@7|||S900|mbit_jak@1|bit|31.5|-3.25|pin@1||31.5|-18
AMetal-1|net@8|||S900|mbit_jak@6|gnd|16.5|105|mbit_jak@4|gnd|16.5|68.75
AMetal-1|net@9|||S900|mbit_jak@4|gnd|15.5|67.75|mbit_jak@2|gnd|15.5|31.5
AMetal-1|net@10|||S900|mbit_jak@2|gnd|16|30.5|mbit_jak@0|gnd|16|-6
AMetal-1|net@11|||S900|mbit_jak@0|gnd|16|-6.25|contact@1||16|-17.75
AMetal-1|net@12|||S900|mbit_jak@7|gnd|46|105|mbit_jak@5|gnd|46|68.75
AMetal-1|net@13|||S900|mbit_jak@5|gnd|46|67.75|mbit_jak@3|gnd|46|31.5
AMetal-1|net@14|||S900|mbit_jak@3|gnd|46|30.5|mbit_jak@1|gnd|46|-5.75
AMetal-1|net@15|||S900|mbit_jak@1|gnd|45.5|-6.25|contact@0||45.5|-18
AMetal-2|net@16|||S1800|pin@4||39|-18|contact@0||45.5|-18
AMetal-2|net@17|||S0|pin@5||21|-18|contact@1||16|-18
AMetal-2|net@18|||S900|pin@5||21|-18|pin@6||21|-18
AMetal-2|net@19|||S1800|pin@6||21|-18|pin@4||39|-18
AMetal-2|net@20|||S1800|pin@7||-13.5|-18|pin@8||16|-18
AMetal-2|net@21|||S900|pin@8||16|-18|contact@1||16|-18
APolysilicon-1|net@23|||S0|mbit_jak@0|wl|-5|1.5|pin@9||-14.25|1.5
APolysilicon-1|net@24|||S0|mbit_jak@2|wl|-5|38.75|pin@10||-15.25|38.75
APolysilicon-1|net@25|||S0|mbit_jak@4|wl|-5|76|pin@11||-15.75|76
APolysilicon-1|net@26|||S0|mbit_jak@6|wl|-5|113.25|pin@12||-15|113.25
APolysilicon-1|net@27||8|IJS1800|mbit_jak@0|vdd_1|9|11.5|mbit_jak@1|vdd|24.5|11.5
APolysilicon-1|net@29|||S1800|mbit_jak@2|vdd_1|9|48.5|mbit_jak@3|vdd|24.5|48.5
APolysilicon-1|net@30|||S0|mbit_jak@2|vdd|-5|48.75|pin@14||-15.75|48.75
APolysilicon-1|net@32|||S1800|mbit_jak@6|vdd_1|9|123.5|mbit_jak@7|vdd|24.5|123.5
APolysilicon-1|net@33|||S1800|mbit_jak@4|vdd_1|9|86.25|mbit_jak@5|vdd|24.5|86.25
APolysilicon-1|net@34|||S0|mbit_jak@4|vdd|-5|86|pin@16||-17|86
APolysilicon-1|net@35|||S0|mbit_jak@6|vdd|-5|123.25|pin@17||-15.75|123.25
APolysilicon-1|net@36|||S1800|contact@2||-20.5|123.25|pin@18||-15.75|123.25
APolysilicon-1|net@37|||S900|pin@18||-15.75|123.25|pin@17||-15.75|123.25
APolysilicon-1|net@38|||S1800|contact@3||-21.5|86|pin@19||-17|86
APolysilicon-1|net@39|||S900|pin@19||-17|86|pin@16||-17|86
APolysilicon-1|net@41|||S900|pin@20||-15.75|48.75|pin@14||-15.75|48.75
APolysilicon-1|net@44|||S0|contact@5||-20.25|12|pin@22||-20.5|12
APolysilicon-1|net@48|||S0|pin@20||-15.75|48.75|contact@4||-21.75|48.75
AMetal-1|net@49|||S900|contact@4||-21.75|49.25|pin@24||-21.75|12
AMetal-1|net@50|||S1800|pin@24||-21.75|12|contact@5||-20.25|12
AMetal-1|net@51|||S0|contact@3||-21.5|86.25|pin@25||-21.75|86.25
AMetal-1|net@52|||S900|pin@25||-21.75|86.25|contact@4||-21.75|49.25
AMetal-1|net@53|||S0|contact@2||-20.5|123.75|pin@26||-21.5|123.75
AMetal-1|net@54|||S900|pin@26||-21.5|123.75|contact@3||-21.5|86.25
APolysilicon-1|net@57|||S1800|mbit_jak@0|wl_1|9|1.5|mbit_jak@1|wl|24.5|1.5
APolysilicon-1|net@58|||S1800|mbit_jak@2|wl_1|9|38.75|mbit_jak@3|wl|24.5|38.75
APolysilicon-1|net@59|||S1800|mbit_jak@4|wl_1|9|76|mbit_jak@5|wl|24.5|76
APolysilicon-1|net@60|||S1800|mbit_jak@6|wl_1|9|113.25|mbit_jak@7|wl|24.5|113.25
AMetal-1|net@64|||S1800|pin@27||-26.25|11.75|pin@28||-20.25|11.75
AMetal-1|net@65|||S2700|pin@28||-20.25|11.75|contact@5||-20.25|12
APolysilicon-1|net@66|||S0|mbit_jak@0|vdd|-5|12|pin@22||-20.5|12
Eb0||D5G2;|pin@0||B
Eb1||D5G2;|pin@1||B
Egnd||D5G2;|pin@7||G
Evdd||D5G2;|pin@27||P
Ewl0|w0|D5G2;|pin@9||B
Ewl1|w1|D5G2;|pin@10||B
Ewl2|w2|D5G2;|pin@11||B
Ewl3|w3|D5G2;|pin@12||B
X

# Cell array_jake;1{sch}
Carray_jake;1{sch}||schematic|1220923121702|1220923442948|
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||1|-3.5|||R|
NOff-Page|conn@1||9|-3.25|||R|
NOff-Page|conn@2||15|-3.25|||R|
NOff-Page|conn@6||-5.75|3.75||||
NOff-Page|conn@7||-5.75|9.5||||
NOff-Page|conn@8||-5.75|16.75||||
NOff-Page|conn@9||-5.75|22.5||||
Imbit_jake;1{ic}|mbit_jak@0||4.5|2.25|||D5G4;
Imbit_jake;1{ic}|mbit_jak@1||4.5|8|||D5G4;
Imbit_jake;1{ic}|mbit_jak@2||18.5|2.25|||D5G4;
Imbit_jake;1{ic}|mbit_jak@3||18.5|8|||D5G4;
Imbit_jake;1{ic}|mbit_jak@4||4.5|15.25|||D5G4;
Imbit_jake;1{ic}|mbit_jak@5||4.5|21|||D5G4;
Imbit_jake;1{ic}|mbit_jak@6||18.5|15.25|||D5G4;
Imbit_jake;1{ic}|mbit_jak@7||18.5|21|||D5G4;
NWire_Pin|pin@4||23|-0.75||||
NWire_Pin|pin@5||9|-0.75||||
Awire|net@0|||900|mbit_jak@1|bit|1|6.5|mbit_jak@0|bit|1|0.75
Awire|net@1|||900|mbit_jak@1|vdd|9|6.5|mbit_jak@0|vdd|9|0.75
Awire|net@4|||900|mbit_jak@3|bit|15|6.5|mbit_jak@2|bit|15|0.75
Awire|net@5|||900|mbit_jak@3|vdd|23|6.5|mbit_jak@2|vdd|23|0.75
Awire|net@10|||2700|conn@0|y|1|-1.5|mbit_jak@0|bit|1|0.75
Awire|net@11|||2700|pin@5||9|-0.75|mbit_jak@0|vdd|9|0.75
Awire|net@12|||2700|conn@2|y|15|-1.25|mbit_jak@2|bit|15|0.75
Awire|net@13|||900|mbit_jak@2|vdd|23|0.75|pin@4||23|-0.75
Awire|net@14|||2700|conn@1|y|9|-1.25|pin@5||9|-0.75
Awire|net@15|||0|pin@4||23|-0.75|pin@5||9|-0.75
Awire|net@20|||900|mbit_jak@7|bit|15|19.5|mbit_jak@6|bit|15|13.75
Awire|net@21|||900|mbit_jak@7|vdd|23|19.5|mbit_jak@6|vdd|23|13.75
Awire|net@26|||900|mbit_jak@5|bit|1|19.5|mbit_jak@4|bit|1|13.75
Awire|net@27|||900|mbit_jak@5|vdd|9|19.5|mbit_jak@4|vdd|9|13.75
Awire|net@33|||2700|mbit_jak@3|vdd|23|6.5|mbit_jak@6|vdd|23|13.75
Awire|net@34|||900|mbit_jak@6|bit|15|13.75|mbit_jak@3|bit|15|6.5
Awire|net@35|||900|mbit_jak@4|bit|1|13.75|mbit_jak@1|bit|1|6.5
Awire|net@36|||0|mbit_jak@2|wl|18.5|3.75|mbit_jak@0|wl|4.5|3.75
Awire|net@37|||0|mbit_jak@7|wl|18.5|22.5|mbit_jak@5|wl|4.5|22.5
Awire|net@38|||0|mbit_jak@6|wl|18.5|16.75|mbit_jak@4|wl|4.5|16.75
Awire|net@39|||900|mbit_jak@4|vdd|9|13.75|mbit_jak@1|vdd|9|6.5
Awire|net@45|||0|mbit_jak@0|wl|4.5|3.75|conn@6|y|-3.75|3.75
Awire|net@46|||0|mbit_jak@3|wl|18.5|9.5|mbit_jak@1|wl|4.5|9.5
Awire|net@48|||1800|conn@9|y|-3.75|22.5|mbit_jak@5|wl|4.5|22.5
Awire|net@49|||0|mbit_jak@4|wl|4.5|16.75|conn@8|y|-3.75|16.75
Awire|net@50|||0|mbit_jak@1|wl|4.5|9.5|conn@7|y|-3.75|9.5
Ebl|b0|D5G2;X1.25;|conn@0|a|B
Eb1||D5G2;X1;|conn@2|a|B
Evdd||D5G2;RRRX1.75;|conn@1|a|P
Ew0||D5G2;X1.5;|conn@6|a|B
Ew1||D5G2;X1.5;|conn@7|a|B
Ew2||D5G2;X1.5;|conn@8|a|B
Ew3||D5G2;X1.5;|conn@9|a|B
X

# Cell bit_line;1{lay}
Cbit_line;1{lay}||mocmos|1219712812359|1219713948041||DRC_last_good_drc_area_date()G1219713945484
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-Node|plnode@0||3.5|4|3|4000||
NMetal-1-Node|plnode@1||9.5|4|3|4000||
X

# Cell fig16.8;1{sch}
Cfig16.8;1{sch}||schematic|1181669765843|1208961153687|
NCapacitor|C_col_array0|D5G1;X-5;|-20.75|-9|||||SCHEM_capacitance(D5G1;)S100f
NCapacitor|C_col_array1|D5G1;X5.25;|6|-9.25|||||SCHEM_capacitance(D5G1;)S100f
NTransistor|M1|D5G1;X1;Y-3;|-12.5|-13.5|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|-2.5|-13.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|ME1|D5G1;X1;Y-3;|-12.5|0.5|||X||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1.75;Y-2.75;)SN_50n
NTransistor|ME2|D5G1;X1;Y-3;|-2.5|0.5|||X||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1.75;Y-2.5;)SN_50n
NTransistor|ME3|D5G1;X1;Y-3;|-7.25|4.25|||RR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-2.5;)SN_50n
NTransistor|MPD|D5G1;X1;Y-3;|-9.25|-21|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-20.75|-12.75||||
NGround|gnd@1||6|-12.75||||
NGround|gnd@2||-7.25|-25.25||||
NWire_Pin|pin@0||-7.25|2.25||||
NWire_Pin|pin@2||-12.5|2.25||||
NWire_Pin|pin@3||-2.5|2.25||||
NWire_Pin|pin@5||-20|2.25||||
NWire_Pin|pin@8||-14.5|-17.75||||
NWire_Pin|pin@9||-0.5|-17.75||||
NWire_Pin|pin@10||-7.25|-17.75||||
NWire_Pin|pin@11||-14.5|-7||||
NWire_Pin|pin@12||-0.5|-7.25||||
NWire_Pin|pin@14||-19.5|-21||||
NWire_Pin|pin@15||-7.25|-1.5||||
NWire_Pin|pin@16||-7.25|-5.25||||
NWire_Pin|pin@17||-8.5|-13.5||||
NWire_Pin|pin@18||-8.5|-10.75||||
NWire_Pin|pin@19||-0.5|-10.75||||
NWire_Pin|pin@20||-6.5|-13.5||||
NWire_Pin|pin@21||-6.5|-9.75||||
NWire_Pin|pin@22||-14.5|-9.75||||
NWire_Pin|pin@24||-14.5|12.5||||
NWire_Pin|pin@25||-0.5|12.5||||
NWire_Pin|pin@26||-14.5|6.25||||
Ngeneric:Invisible-Pin|pin@29||-28|-2|||||SIM_spice_card(D5G1;)S[VVDD/2  VDD/2  0 DC .5,VEq Eq 0 DC 0 PULSE 0 1 5n 0 0 4n,Vsense sense_N  0 DC 0,.ic v(bitline0)=250m v(bitline1)=750m,.include cmosedu_models.txt,.tran 10p 10n uic,.options post]
NWire_Pin|pin@30||-0.5|6.25||||
Ngeneric:Invisible-Pin|pin@32||-7.25|14.25|||||ART_message(D5G1.5;)SPlot Eq,bitline0 and bitline1
Awire|Eq|D5G1;X-4.75;Y0.75;||1800|pin@5||-20|2.25|pin@2||-12.5|2.25
Awire|NLAT|D5G1;X3.25;Y1;||1800|pin@8||-14.5|-17.75|pin@10||-7.25|-17.75
Awire|VDD/2|D5G1;X0.25;Y-2.75;||900|pin@15||-7.25|-1.5|pin@16||-7.25|-5.25
Awire|bitline0|D5G1;X-1.75;||2700|pin@26||-14.5|6.25|pin@24||-14.5|12.5
Awire|bitline1|D5G1;X1.75;Y0.25;||900|pin@25||-0.5|12.5|pin@30||-0.5|6.25
Awire|net@0|||900|ME3|g|-7.25|3.25|pin@0||-7.25|2.25
Awire|net@1|||0|pin@0||-7.25|2.25|pin@2||-12.5|2.25
Awire|net@3|||2700|ME1|g|-12.5|1.5|pin@2||-12.5|2.25
Awire|net@4|||1800|pin@0||-7.25|2.25|pin@3||-2.5|2.25
Awire|net@5|||900|pin@3||-2.5|2.25|ME2|g|-2.5|1.5
Awire|net@9|||2700|pin@22||-14.5|-9.75|pin@11||-14.5|-7
Awire|net@10|||2700|pin@19||-0.5|-10.75|pin@12||-0.5|-7.25
Awire|net@12|||900|M1|s|-14.5|-15.5|pin@8||-14.5|-17.75
Awire|net@14|||2700|pin@9||-0.5|-17.75|M2|s|-0.5|-15.5
Awire|net@15|||1800|pin@10||-7.25|-17.75|pin@9||-0.5|-17.75
Awire|net@16|||2700|MPD|d|-7.25|-19|pin@10||-7.25|-17.75
Awire|net@17|||900|gnd@0||-20.75|-10.75|C_col_array0|b|-20.75|-11
Awire|net@18|||2700|pin@11||-14.5|-7|ME1|d|-14.5|-1.5
Awire|net@19|||1800|C_col_array0|a|-20.75|-7|pin@11||-14.5|-7
Awire|net@21|||0|C_col_array1|a|6|-7.25|pin@12||-0.5|-7.25
Awire|net@22|||900|gnd@1||6|-10.75|C_col_array1|b|6|-11.25
Awire|net@23|||2700|gnd@2||-7.25|-23.25|MPD|s|-7.25|-23
Awire|net@27|||1800|pin@15||-7.25|-1.5|ME2|d|-4.5|-1.5
Awire|net@29|||1800|M1|g|-11.5|-13.5|pin@17||-8.5|-13.5
Awire|net@30|||2700|pin@17||-8.5|-13.5|pin@18||-8.5|-10.75
Awire|net@31|||2700|M2|d|-0.5|-11.5|pin@19||-0.5|-10.75
Awire|net@32|||1800|pin@18||-8.5|-10.75|pin@19||-0.5|-10.75
Awire|net@33|||0|M2|g|-3.5|-13.5|pin@20||-6.5|-13.5
Awire|net@34|||2700|pin@20||-6.5|-13.5|pin@21||-6.5|-9.75
Awire|net@36|||0|pin@21||-6.5|-9.75|pin@22||-14.5|-9.75
Awire|net@40|||2700|ME1|d|-14.5|-1.5|pin@26||-14.5|6.25
Awire|net@41|||0|ME3|d|-9.25|6.25|pin@26||-14.5|6.25
Awire|net@44|||1800|ME1|s|-10.5|-1.5|pin@15||-7.25|-1.5
Awire|net@45|||2700|M1|d|-14.5|-11.5|pin@22||-14.5|-9.75
Awire|net@54|||900|ME2|s|-0.5|-1.5|pin@12||-0.5|-7.25
Awire|net@56|||900|pin@30||-0.5|6.25|ME2|s|-0.5|-1.5
Awire|net@57|||1800|ME3|s|-5.25|6.25|pin@30||-0.5|6.25
Awire|net@60|||900|pin@25||-0.5|12.5|pin@12||-0.5|-7.25
Awire|sense_N|D5G1;X-7;Y0.75;||0|MPD|g|-10.25|-21|pin@14||-19.5|-21
X

# Cell fig16.11;1{sch}
Cfig16.11;1{sch}||schematic|1181671368515|1208961182562|
NCapacitor|C_col_array0|D5G1;X-5.25;|-11.5|-5.75|||||SCHEM_capacitance(D5G1;)S100f
NCapacitor|C_col_array1|D5G1;X4.5;|15.25|-6|||||SCHEM_capacitance(D5G1;)S100f
NCapacitor|C_mbit0|D5G1;X-5.25;|-9|16|||||SCHEM_capacitance(D5G1;)S20f
NCapacitor|C_mbit1|D5G1;X-5.25;|23|-23.5|||||SCHEM_capacitance(D5G1;)S20f
NTransistor|M1|D5G1;X1;Y-3;|-3.25|-10.25|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|6.75|-10.25|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|ME1|D5G1;X1;Y-3;|-3.25|3.75|||X||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1.75;Y-2.75;)SN_50n
NTransistor|ME2|D5G1;X1;Y-3;|6.75|3.75|||X||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1.75;Y-2.5;)SN_50n
NTransistor|ME3|D5G1;X1;Y-3;|2|7.5|||RR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-2.5;)SN_50n
NTransistor|MPD|D5G1;X1;Y-3;|0|-17.75|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|Mbit0|D5G1;X1;Y-3;|-11|22.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|Mbit1|D5G1;X1;Y-3;|21|-17|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-11.5|-9.5||||
NGround|gnd@1||15.25|-9.5||||
NGround|gnd@2||2|-22||||
NGround|gnd@5||-9|12.25||||
NGround|gnd@6||23|-28.25||||
NWire_Pin|pin@0||2|5.5||||
NWire_Pin|pin@1||2|-14.5||||
NWire_Pin|pin@2||-3.25|5.5||||
NWire_Pin|pin@3||2.75|-10.25||||
NWire_Pin|pin@4||2.75|-6.5||||
NWire_Pin|pin@5||-5.25|-6.5||||
NWire_Pin|pin@8||-5.25|9.5||||
Ngeneric:Invisible-Pin|pin@9||-24|5.25|||||SIM_spice_card(D5G1;)S[VVDD/2  VDD/2  0 DC .5,VGND GND 0 DC 0,VEq Eq 0 DC 0 PULSE 0 1 5n 0 0 4n,Vsense sense_N 0 DC 0 PULSE 0 1 15n,Vra0 ra0 0 dc 0 pulse 0 1.5 12n,Vra1 ra1 0 dc 0,.ic v(bitline0)=250m v(bitline1)=750m V(mb0)=0,.include cmosedu_models.txt,.tran 10p 20n,.options post]
NWire_Pin|pin@10||6.75|5.5||||
NWire_Pin|pin@11||8.75|9.5||||
NWire_Pin|pin@12||-5.25|-3.75||||
Ngeneric:Invisible-Pin|pin@13||7|28.5|||R||ART_message(D5G2;RRR)SPlot Eq,bitline0, bitline1,ra0 and sense_N
NWire_Pin|pin@14||-10.75|5.5||||
NWire_Pin|pin@15||-5.25|-14.5||||
NWire_Pin|pin@16||8.75|-14.5||||
NWire_Pin|pin@17||8.75|-4||||
NWire_Pin|pin@18||-10.25|-17.75||||
NWire_Pin|pin@19||2.25|1.75||||
NWire_Pin|pin@20||2.25|-2||||
NWire_Pin|pin@21||0.75|-10.25||||
NWire_Pin|pin@22||0.75|-7.5||||
NWire_Pin|pin@23||8.75|-7.5||||
NWire_Pin|pin@24||-19.75|22.5||||
NWire_Pin|pin@25||-9|26.5||||
NWire_Pin|pin@27||-5.25|26.5||||
NWire_Pin|pin@28||10.75|-17||||
NWire_Pin|pin@30||8.75|17.75||||
NWire_Pin|pin@32||23|17.75||||
Ngeneric:Invisible-Pin|pin@34||-19.75|23.5|||||ART_message(D5G1;)Swordline in array0
Ngeneric:Invisible-Pin|pin@35||14.5|-17.75|||||ART_message(D5G1;)Swordline in array1
Awire|Eq|D5G1;X-4.75;Y0.75;||1800|pin@14||-10.75|5.5|pin@2||-3.25|5.5
Awire|NLAT|D5G1;X3.25;Y1;||1800|pin@15||-5.25|-14.5|pin@1||2|-14.5
Awire|VDD/2|D5G1;X0.25;Y-2.75;||900|pin@19||2.25|1.75|pin@20||2.25|-2
Awire|bitline0|D5G1;X0.25;Y-19;||2700|pin@8||-5.25|9.5|pin@27||-5.25|26.5
Awire|bitline1|D5G1;X0.25;Y-14.75;||900|pin@30||8.75|17.75|pin@11||8.75|9.5
Awire|mb0|D5G1;||2700|C_mbit0|a|-9|18|Mbit0|s|-9|20.5
Awire|mb1|D5G1;||2700|C_mbit1|a|23|-21.5|Mbit1|s|23|-19
Awire|net@0|||900|ME3|g|2|6.5|pin@0||2|5.5
Awire|net@1|||0|pin@0||2|5.5|pin@2||-3.25|5.5
Awire|net@2|||0|C_col_array1|a|15.25|-4|pin@17||8.75|-4
Awire|net@3|||900|gnd@1||15.25|-7.5|C_col_array1|b|15.25|-8
Awire|net@4|||2700|gnd@2||2|-20|MPD|s|2|-19.75
Awire|net@5|||1800|pin@19||2.25|1.75|ME2|d|4.75|1.75
Awire|net@6|||1800|M1|g|-2.25|-10.25|pin@21||0.75|-10.25
Awire|net@7|||2700|ME1|g|-3.25|4.75|pin@2||-3.25|5.5
Awire|net@8|||2700|pin@21||0.75|-10.25|pin@22||0.75|-7.5
Awire|net@9|||2700|M2|d|8.75|-8.25|pin@23||8.75|-7.5
Awire|net@10|||1800|pin@22||0.75|-7.5|pin@23||8.75|-7.5
Awire|net@11|||0|M2|g|5.75|-10.25|pin@3||2.75|-10.25
Awire|net@12|||2700|pin@23||8.75|-7.5|pin@17||8.75|-4
Awire|net@13|||2700|pin@3||2.75|-10.25|pin@4||2.75|-6.5
Awire|net@14|||0|pin@4||2.75|-6.5|pin@5||-5.25|-6.5
Awire|net@15|||1800|pin@0||2|5.5|pin@10||6.75|5.5
Awire|net@16|||2700|ME1|d|-5.25|1.75|pin@8||-5.25|9.5
Awire|net@17|||0|ME3|d|0|9.5|pin@8||-5.25|9.5
Awire|net@18|||1800|ME1|s|-1.25|1.75|pin@19||2.25|1.75
Awire|net@19|||2700|M1|d|-5.25|-8.25|pin@5||-5.25|-6.5
Awire|net@20|||900|pin@10||6.75|5.5|ME2|g|6.75|4.75
Awire|net@21|||900|ME2|s|8.75|1.75|pin@17||8.75|-4
Awire|net@22|||900|pin@11||8.75|9.5|ME2|s|8.75|1.75
Awire|net@23|||900|M1|s|-5.25|-12.25|pin@15||-5.25|-14.5
Awire|net@24|||1800|ME3|s|4|9.5|pin@11||8.75|9.5
Awire|net@26|||2700|pin@5||-5.25|-6.5|pin@12||-5.25|-3.75
Awire|net@27|||2700|pin@16||8.75|-14.5|M2|s|8.75|-12.25
Awire|net@28|||1800|pin@1||2|-14.5|pin@16||8.75|-14.5
Awire|net@29|||2700|MPD|d|2|-15.75|pin@1||2|-14.5
Awire|net@30|||900|gnd@0||-11.5|-7.5|C_col_array0|b|-11.5|-7.75
Awire|net@31|||2700|pin@12||-5.25|-3.75|ME1|d|-5.25|1.75
Awire|net@32|||1800|C_col_array0|a|-11.5|-3.75|pin@12||-5.25|-3.75
Awire|net@35|||2700|Mbit0|d|-9|24.5|pin@25||-9|26.5
Awire|net@38|||1800|pin@25||-9|26.5|pin@27||-5.25|26.5
Awire|net@46|||900|gnd@5||-9|14.25|C_mbit0|b|-9|14
Awire|net@48|||2700|gnd@6||23|-26.25|C_mbit1|b|23|-25.5
Awire|net@51|||900|pin@32||23|17.75|Mbit1|d|23|-15
Awire|net@52|||1800|pin@30||8.75|17.75|pin@32||23|17.75
Awire|ra0|D5G1;X2;Y0.75;||0|Mbit0|g|-12|22.5|pin@24||-19.75|22.5
Awire|ra1|D5G1;X-1.5;Y0.75;||0|Mbit1|g|20|-17|pin@28||10.75|-17
Awire|sense_N|D5G1;X-7;Y0.75;||0|MPD|g|-1|-17.75|pin@18||-10.25|-17.75
X

# Cell fig16.12;1{sch}
Cfig16.12;1{sch}||schematic|1181672529781|1208961200453|
NCapacitor|C_col_array0|D5G1;X-5.25;|-16.5|-8.5|||||SCHEM_capacitance(D5G1;)S100f
NCapacitor|C_col_array1|D5G1;X5;|10.25|-8.75|||||SCHEM_capacitance(D5G1;)S100f
NCapacitor|C_mbit0|D5G1;X-5.25;|-14|13.25|||||SCHEM_capacitance(D5G1;)S20f
NCapacitor|C_mbit1|D5G1;X-5.25;|22.25|-26.25|||||SCHEM_capacitance(D5G1;)S20f
NTransistor|M1|D5G1;X1;Y-3;|-8.25|-13|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|1.75|-13|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|ME1|D5G1;X1;Y-3;|-8.25|1|||X||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1.75;Y-2.75;)SN_50n
NTransistor|ME2|D5G1;X1;Y-3;|1.75|1|||X||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1.75;Y-2.5;)SN_50n
NTransistor|ME3|D5G1;X1;Y-3;|-3|4.75|||RR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-2.5;)SN_50n
NTransistor|MPD|D5G1;X1;Y-3;|-5|-20.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|Mbit0|D5G1;X1;Y-3;|-16|19.75|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|Mbit1|D5G1;X1;Y-3;|20.25|-19.75|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-14|9.5||||
NGround|gnd@1||22.25|-31||||
NGround|gnd@2||-16.5|-12.25||||
NGround|gnd@3||10.25|-12.25||||
NGround|gnd@4||-3|-24.75||||
NWire_Pin|pin@0||-3|2.75||||
NWire_Pin|pin@1||-3|-17.25||||
NWire_Pin|pin@2||1.75|2.75||||
NWire_Pin|pin@3||3.75|6.75||||
NWire_Pin|pin@4||-10.25|-6.5||||
Ngeneric:Invisible-Pin|pin@5||3.75|25.5|||R||ART_message(D5G2;RRR)SPlot Eq,bitline0, bitline1,ra0 and sense_N
NWire_Pin|pin@6||-15.75|2.75||||
NWire_Pin|pin@7||-10.25|-17.25||||
NWire_Pin|pin@8||3.75|-17.25||||
NWire_Pin|pin@9||3.75|-6.75||||
NWire_Pin|pin@10||-15.25|-20.5||||
NWire_Pin|pin@11||-2.75|-1||||
NWire_Pin|pin@12||-8.25|2.75||||
NWire_Pin|pin@13||-2.75|-4.75||||
NWire_Pin|pin@14||-4.25|-13||||
NWire_Pin|pin@15||-4.25|-10.25||||
NWire_Pin|pin@16||3.75|-10.25||||
NWire_Pin|pin@17||-24.75|19.75||||
NWire_Pin|pin@18||-14|23.75||||
NWire_Pin|pin@19||-10.25|23.75||||
NWire_Pin|pin@20||10|-19.75||||
NWire_Pin|pin@21||-2.25|-13||||
NWire_Pin|pin@22||3.75|15||||
NWire_Pin|pin@23||22.25|15||||
Ngeneric:Invisible-Pin|pin@24||-24.75|20.75|||||ART_message(D5G1;)Swordline in array0
Ngeneric:Invisible-Pin|pin@25||13.75|-20.5|||||ART_message(D5G1;)Swordline in array1
NWire_Pin|pin@26||-2.25|-9.25||||
NWire_Pin|pin@27||-10.25|-9.25||||
NWire_Pin|pin@29||-10.25|6.75||||
Ngeneric:Invisible-Pin|pin@30||-28.25|2.25|||||SIM_spice_card(D5G1;)S[VVDD/2  VDD/2  0 DC .5,VGND GND 0 DC 0,VEq Eq 0 DC 0 PULSE 0 1 5n 0 0 4n,Vsense sense_N 0 DC 0 PULSE 0 1 15n,Vra0 ra0 0 dc 0 pulse 0 1.5 12n,Vra1 ra1 0 dc 0,.ic v(bitline0)=250m v(bitline1)=750m V(mb0)=1,.include cmosedu_models.txt,.tran  10p 20n,.options post]
Awire|Eq|D5G1;X-4.75;Y0.75;||1800|pin@6||-15.75|2.75|pin@12||-8.25|2.75
Awire|NLAT|D5G1;X3.25;Y1;||1800|pin@7||-10.25|-17.25|pin@1||-3|-17.25
Awire|VDD/2|D5G1;X0.25;Y-2.75;||900|pin@11||-2.75|-1|pin@13||-2.75|-4.75
Awire|bitline0|D5G1;X0.25;Y-19;||2700|pin@29||-10.25|6.75|pin@19||-10.25|23.75
Awire|bitline1|D5G1;X0.25;Y-14.75;||900|pin@22||3.75|15|pin@3||3.75|6.75
Awire|mb0|D5G1;||2700|C_mbit0|a|-14|15.25|Mbit0|s|-14|17.75
Awire|mb1|D5G1;||2700|C_mbit1|a|22.25|-24.25|Mbit1|s|22.25|-21.75
Awire|net@0|||900|ME3|g|-3|3.75|pin@0||-3|2.75
Awire|net@1|||0|pin@0||-3|2.75|pin@12||-8.25|2.75
Awire|net@2|||1800|pin@15||-4.25|-10.25|pin@16||3.75|-10.25
Awire|net@3|||0|M2|g|0.75|-13|pin@21||-2.25|-13
Awire|net@4|||2700|pin@16||3.75|-10.25|pin@9||3.75|-6.75
Awire|net@5|||2700|pin@21||-2.25|-13|pin@26||-2.25|-9.25
Awire|net@6|||0|pin@26||-2.25|-9.25|pin@27||-10.25|-9.25
Awire|net@7|||1800|pin@0||-3|2.75|pin@2||1.75|2.75
Awire|net@8|||2700|ME1|d|-10.25|-1|pin@29||-10.25|6.75
Awire|net@9|||0|ME3|d|-5|6.75|pin@29||-10.25|6.75
Awire|net@10|||1800|ME1|s|-6.25|-1|pin@11||-2.75|-1
Awire|net@11|||2700|M1|d|-10.25|-11|pin@27||-10.25|-9.25
Awire|net@12|||0|C_col_array1|a|10.25|-6.75|pin@9||3.75|-6.75
Awire|net@13|||900|pin@2||1.75|2.75|ME2|g|1.75|2
Awire|net@14|||900|ME2|s|3.75|-1|pin@9||3.75|-6.75
Awire|net@15|||900|pin@3||3.75|6.75|ME2|s|3.75|-1
Awire|net@16|||900|M1|s|-10.25|-15|pin@7||-10.25|-17.25
Awire|net@17|||1800|ME3|s|-1|6.75|pin@3||3.75|6.75
Awire|net@19|||2700|pin@27||-10.25|-9.25|pin@4||-10.25|-6.5
Awire|net@20|||2700|pin@8||3.75|-17.25|M2|s|3.75|-15
Awire|net@21|||1800|pin@1||-3|-17.25|pin@8||3.75|-17.25
Awire|net@22|||2700|MPD|d|-3|-18.5|pin@1||-3|-17.25
Awire|net@23|||900|gnd@3||10.25|-10.25|C_col_array1|b|10.25|-10.75
Awire|net@24|||900|gnd@2||-16.5|-10.25|C_col_array0|b|-16.5|-10.5
Awire|net@25|||2700|pin@4||-10.25|-6.5|ME1|d|-10.25|-1
Awire|net@26|||1800|C_col_array0|a|-16.5|-6.5|pin@4||-10.25|-6.5
Awire|net@27|||2700|Mbit0|d|-14|21.75|pin@18||-14|23.75
Awire|net@28|||1800|pin@18||-14|23.75|pin@19||-10.25|23.75
Awire|net@29|||2700|gnd@4||-3|-22.75|MPD|s|-3|-22.5
Awire|net@31|||900|gnd@0||-14|11.5|C_mbit0|b|-14|11.25
Awire|net@32|||2700|gnd@1||22.25|-29|C_mbit1|b|22.25|-28.25
Awire|net@33|||1800|pin@11||-2.75|-1|ME2|d|-0.25|-1
Awire|net@34|||900|pin@23||22.25|15|Mbit1|d|22.25|-17.75
Awire|net@35|||1800|pin@22||3.75|15|pin@23||22.25|15
Awire|net@36|||1800|M1|g|-7.25|-13|pin@14||-4.25|-13
Awire|net@37|||2700|ME1|g|-8.25|2|pin@12||-8.25|2.75
Awire|net@38|||2700|pin@14||-4.25|-13|pin@15||-4.25|-10.25
Awire|net@39|||2700|M2|d|3.75|-11|pin@16||3.75|-10.25
Awire|ra0|D5G1;X2;Y0.75;||0|Mbit0|g|-17|19.75|pin@17||-24.75|19.75
Awire|ra1|D5G1;X-1.5;Y0.75;||0|Mbit1|g|19.25|-19.75|pin@20||10|-19.75
Awire|sense_N|D5G1;X-7;Y0.75;||0|MPD|g|-6|-20.5|pin@10||-15.25|-20.5
X

# Cell fig16.14;2{sch}
Cfig16.14;2{sch}||schematic|1181672674906|1208961214046|
NCapacitor|C_col_array0|D5G1;X-5.25;|-17|-5.5|||||SCHEM_capacitance(D5G1;)S100f
NCapacitor|C_col_array1|D5G1;X5;|9.75|-5.75|||||SCHEM_capacitance(D5G1;)S100f
NCapacitor|C_mbit0|D5G1;X-5.25;|-14.75|31|||||SCHEM_capacitance(D5G1;)S20f
NCapacitor|C_mbit1|D5G1;X-5.25;|21.75|-23.25|||||SCHEM_capacitance(D5G1;)S20f
NTransistor|M1|D5G1;X1;Y-3;|-9|-10|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|1.25|-10|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|ME1|D5G1;X1;Y-3;|-9|4|||X||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1.75;Y-2.75;)SN_50n
NTransistor|ME2|D5G1;X1;Y-3;|1.25|4|||X||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1.75;Y-2.5;)SN_50n
NTransistor|ME3|D5G1;X1;Y-3;|-3.5|7.75|||RR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-2.5;)SN_50n
NTransistor|MPD|D5G1;X1;Y-3;|-5.5|-17.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|Mbit0|D5G1;X1;Y-3;|-16.75|37.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|Mbit1|D5G1;X1;Y-3;|19.75|-16.75|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-14.75|27.25||||
NGround|gnd@1||21.75|-28||||
NGround|gnd@2||-17|-9.25||||
NGround|gnd@3||9.75|-9.25||||
NGround|gnd@4||-3.5|-21.75||||
NWire_Pin|pin@0||-3.5|5.75||||
NWire_Pin|pin@1||-3.5|-14.25||||
NWire_Pin|pin@2||-15.75|-17.5||||
NWire_Pin|pin@3||-3.25|2||||
NWire_Pin|pin@4||-9|5.75||||
NWire_Pin|pin@5||-3.25|-1.75||||
NWire_Pin|pin@6||-4.75|-10||||
NWire_Pin|pin@7||-4.75|-7.25||||
NWire_Pin|pin@8||3.25|-7.25||||
NWire_Pin|pin@9||-25.5|37.5||||
NWire_Pin|pin@10||-14.75|41.5||||
NWire_Pin|pin@11||-11|41.5||||
NWire_Pin|pin@12||1.25|5.75||||
NWire_Pin|pin@13||9.5|-16.75||||
NWire_Pin|pin@14||-2.75|-10||||
NWire_Pin|pin@15||3.25|18||||
NWire_Pin|pin@16||21.75|18||||
Ngeneric:Invisible-Pin|pin@17||-25.5|38.5|||||ART_message(D5G1;)Swordline in array0
Ngeneric:Invisible-Pin|pin@18||13.25|-17.5|||||ART_message(D5G1;)Swordline in array1
NWire_Pin|pin@19||-2.75|-6.25||||
NWire_Pin|pin@20||-11|-6.25||||
NWire_Pin|pin@21||3.25|18.25||||
NWire_Pin|pin@22||-11|9.75||||
NWire_Pin|pin@23||3.25|9.75||||
Ngeneric:Invisible-Pin|pin@24||7.25|31|||||SIM_spice_card(D5G1;)S[VGND GND 0 DC 0,VVDD VDD 0 DC 1,VVDD/2  VDD/2  0 DC .5,VEq Eq 0 DC 0 PULSE 0 1 5n 0 0 4n,Vsense sense_N 0 DC 0 PULSE 0 1 15n,VsenseP sense_P 0 DC 0 PULSE 1 0 18n,Vra0 ra0 0 dc 0 pulse 0 1.5 12n,Vra1 ra1 0 dc 0,.ic v(bitline0)=250m v(bitline1)=750m V(mb0)=1,.include cmosedu_models.txt,.tran 10p  30n,.options post]
NWire_Pin|pin@25||-11|-3.5||||
Ngeneric:Invisible-Pin|pin@26||-0.75|44.5|||R||ART_message(D5G2;RRR)SPlot Eq, ra0, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
NWire_Pin|pin@27||-16.25|5.75||||
NWire_Pin|pin@28||-11|-14.25||||
NWire_Pin|pin@29||3.25|-14.25||||
NWire_Pin|pin@30||3.25|-3.75||||
NWire_Pin|pin@31||1|13.75||||
NWire_Pin|pin@34||3.25|13.75||||
NWire_Pin|pin@39||-4.5|17.25||||
NWire_Pin|pin@42||-4.5|13.75||||
NWire_Pin|pin@43||-9.5|13.75||||
NWire_Pin|pin@44||-11|13.75||||
NWire_Pin|pin@48||-2.5|13.75||||
NWire_Pin|pin@49||-2.5|16.75||||
NWire_Pin|pin@51||-9.5|20.25||||
NWire_Pin|pin@53||1|20.25||||
NWire_Pin|pin@55||-26|22.25||||
NTransistor|pmos@0||-7.5|16.75|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|pmos@1||-1|17.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|pmos@2||-23|22.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NPower|pwr@0||-21|26.5||||
Awire|ACT|D5G1;Y0.75;||1800|pin@51||-9.5|20.25|pin@53||1|20.25
Awire|Eq|D5G1;X-4.75;Y0.75;||1800|pin@27||-16.25|5.75|pin@4||-9|5.75
Awire|NLAT|D5G1;X3.25;Y1;||1800|pin@28||-11|-14.25|pin@1||-3.5|-14.25
Awire|VDD/2|D5G1;X0.25;Y-2.75;||900|pin@3||-3.25|2|pin@5||-3.25|-1.75
Awire|bitline0|D5G1;X-0.25;Y-28.75;||900|pin@11||-11|41.5|pin@44||-11|13.75
Awire|bitline1|D5G1;X0.5;Y-13;||900|pin@34||3.25|13.75|pin@23||3.25|9.75
Awire|mb0|D5G1;||2700|C_mbit0|a|-14.75|33|Mbit0|s|-14.75|35.5
Awire|mb1|D5G1;||2700|C_mbit1|a|21.75|-21.25|Mbit1|s|21.75|-18.75
Awire|net@0|||0|M2|g|0.25|-10|pin@14||-2.75|-10
Awire|net@1|||900|pin@21||3.25|18.25|pin@15||3.25|18
Awire|net@2|||900|gnd@0||-14.75|29.25|C_mbit0|b|-14.75|29
Awire|net@3|||2700|gnd@1||21.75|-26|C_mbit1|b|21.75|-25.25
Awire|net@4|||1800|pin@3||-3.25|2|ME2|d|-0.75|2
Awire|net@5|||900|pin@16||21.75|18|Mbit1|d|21.75|-14.75
Awire|net@6|||1800|pin@15||3.25|18|pin@16||21.75|18
Awire|net@7|||1800|M1|g|-8|-10|pin@6||-4.75|-10
Awire|net@8|||2700|ME1|g|-9|5|pin@4||-9|5.75
Awire|net@9|||2700|pin@6||-4.75|-10|pin@7||-4.75|-7.25
Awire|net@10|||2700|M2|d|3.25|-8|pin@8||3.25|-7.25
Awire|net@11|||2700|pin@8||3.25|-7.25|pin@30||3.25|-3.75
Awire|net@12|||2700|pin@14||-2.75|-10|pin@19||-2.75|-6.25
Awire|net@13|||0|pin@19||-2.75|-6.25|pin@20||-11|-6.25
Awire|net@14|||1800|pin@0||-3.5|5.75|pin@12||1.25|5.75
Awire|net@15|||2700|ME1|d|-11|2|pin@22||-11|9.75
Awire|net@16|||0|ME3|d|-5.5|9.75|pin@22||-11|9.75
Awire|net@17|||900|ME3|g|-3.5|6.75|pin@0||-3.5|5.75
Awire|net@18|||0|pin@0||-3.5|5.75|pin@4||-9|5.75
Awire|net@19|||1800|ME1|s|-7|2|pin@3||-3.25|2
Awire|net@20|||2700|M1|d|-11|-8|pin@20||-11|-6.25
Awire|net@21|||0|C_col_array1|a|9.75|-3.75|pin@30||3.25|-3.75
Awire|net@22|||900|pin@12||1.25|5.75|ME2|g|1.25|5
Awire|net@23|||900|ME2|s|3.25|2|pin@30||3.25|-3.75
Awire|net@24|||900|pin@23||3.25|9.75|ME2|s|3.25|2
Awire|net@25|||900|M1|s|-11|-12|pin@28||-11|-14.25
Awire|net@26|||1800|ME3|s|-1.5|9.75|pin@23||3.25|9.75
Awire|net@27|||900|pin@21||3.25|18.25|pin@30||3.25|-3.75
Awire|net@28|||2700|pin@20||-11|-6.25|pin@25||-11|-3.5
Awire|net@29|||1800|pin@7||-4.75|-7.25|pin@8||3.25|-7.25
Awire|net@30|||2700|pin@29||3.25|-14.25|M2|s|3.25|-12
Awire|net@31|||1800|pin@1||-3.5|-14.25|pin@29||3.25|-14.25
Awire|net@32|||2700|MPD|d|-3.5|-15.5|pin@1||-3.5|-14.25
Awire|net@33|||900|gnd@3||9.75|-7.25|C_col_array1|b|9.75|-7.75
Awire|net@34|||900|gnd@2||-17|-7.25|C_col_array0|b|-17|-7.5
Awire|net@35|||2700|pin@25||-11|-3.5|ME1|d|-11|2
Awire|net@36|||1800|C_col_array0|a|-17|-3.5|pin@25||-11|-3.5
Awire|net@37|||2700|Mbit0|d|-14.75|39.5|pin@10||-14.75|41.5
Awire|net@38|||1800|pin@10||-14.75|41.5|pin@11||-11|41.5
Awire|net@39|||2700|gnd@4||-3.5|-19.75|MPD|s|-3.5|-19.5
Awire|net@40|||900|pmos@1|s|1|15.25|pin@31||1|13.75
Awire|net@44|||900|pin@15||3.25|18|pin@34||3.25|13.75
Awire|net@45|||1800|pin@31||1|13.75|pin@34||3.25|13.75
Awire|net@51|||0|pmos@1|g|-2|17.25|pin@39||-4.5|17.25
Awire|net@55|||900|pin@39||-4.5|17.25|pin@42||-4.5|13.75
Awire|net@56|||0|pin@42||-4.5|13.75|pin@43||-9.5|13.75
Awire|net@57|||2700|pin@43||-9.5|13.75|pmos@0|s|-9.5|14.75
Awire|net@58|||2700|pin@22||-11|9.75|pin@44||-11|13.75
Awire|net@59|||0|pin@43||-9.5|13.75|pin@44||-11|13.75
Awire|net@68|||2700|pmos@0|d|-9.5|18.75|pin@51||-9.5|20.25
Awire|net@72|||900|pin@53||1|20.25|pmos@1|d|1|19.25
Awire|net@79|||1800|pmos@0|g|-6.5|16.75|pin@49||-2.5|16.75
Awire|net@81|||900|pin@49||-2.5|16.75|pin@48||-2.5|13.75
Awire|net@82|||0|pin@31||1|13.75|pin@48||-2.5|13.75
Awire|net@85|||900|pwr@0||-21|26.5|pmos@2|d|-21|24.25
Awire|net@86|||1800|pmos@2|s|-21|20.25|pin@51||-9.5|20.25
Awire|ra0|D5G1;X2;Y0.75;||0|Mbit0|g|-17.75|37.5|pin@9||-25.5|37.5
Awire|ra1|D5G1;X-1.5;Y0.75;||0|Mbit1|g|18.75|-16.75|pin@13||9.5|-16.75
Awire|sense_N|D5G1;X-7;Y0.75;||0|MPD|g|-6.5|-17.5|pin@2||-15.75|-17.5
Awire|sense_P|D5G1;X-2.75;Y0.25;||0|pmos@2|g|-24|22.25|pin@55||-26|22.25
X

# Cell fig16.14;1{sch}
Cfig16.14;1{sch}||schematic|1181672674906|1220921034091|
NCapacitor|C_col_array0|D5G1;X-5.25;|-17|-5.5|||||SCHEM_capacitance(D5G1;)S.100f
NCapacitor|C_col_array1|D5G1;X5;|9.75|-5.75|||||SCHEM_capacitance(D5G1;)S.100f
NTransistor|M1|D5G1;X1;Y-3;|-9|-10|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|1.25|-10|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|ME1|D5G1;X1;Y-3;|-9|4|||X||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1.75;Y-2.75;)SN_50n
NTransistor|ME2|D5G1;X1;Y-3;|1.25|4|||X||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1.75;Y-2.5;)SN_50n
NTransistor|ME3|D5G1;X1;Y-3;|-3.5|7.75|||RR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-2.5;)SN_50n
NTransistor|MPD|D5G1;X1;Y-3;|-5.5|-17.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|Mbit0|D5G1;X1;Y-3;|-16.75|37.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|Mbit1|D5G1;X1;Y-3;|19.75|-16.75|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|Mbit2|D5G1;X1;Y-3;|-16.75|32.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D10.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@2||-17|-9.25||||
NGround|gnd@3||9.75|-9.25||||
NGround|gnd@4||-3.5|-21.75||||
NTransistor|nmos@0||19.75|-22|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D10.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-2.25;)SN_50n
NWire_Pin|pin@0||-3.5|5.75||||
NWire_Pin|pin@1||-3.5|-14.25||||
NWire_Pin|pin@2||-15.75|-17.5||||
NWire_Pin|pin@3||-3.25|2||||
NWire_Pin|pin@4||-9|5.75||||
NWire_Pin|pin@5||-3.25|-1.75||||
NWire_Pin|pin@6||-4.75|-10||||
NWire_Pin|pin@7||-4.75|-7.25||||
NWire_Pin|pin@8||3.25|-7.25||||
NWire_Pin|pin@9||-25.5|37.5||||
NWire_Pin|pin@10||-14.75|41.5||||
NWire_Pin|pin@11||-11|41.5||||
NWire_Pin|pin@12||1.25|5.75||||
NWire_Pin|pin@13||9.5|-16.75||||
NWire_Pin|pin@14||-2.75|-10||||
NWire_Pin|pin@15||3.25|18||||
NWire_Pin|pin@16||21.75|18||||
Ngeneric:Invisible-Pin|pin@17||-25.5|38.5|||||ART_message(D5G1;)Swordline in array0
Ngeneric:Invisible-Pin|pin@18||13.25|-17.5|||||ART_message(D5G1;)Swordline in array1
NWire_Pin|pin@19||-2.75|-6.25||||
NWire_Pin|pin@20||-11|-6.25||||
NWire_Pin|pin@21||3.25|18.25||||
NWire_Pin|pin@22||-11|9.75||||
NWire_Pin|pin@23||3.25|9.75||||
Ngeneric:Invisible-Pin|pin@24||7.25|31|||||SIM_spice_card(D5G1;)S[VGND GND 0 DC 0,VVDD VDD 0 DC 1,VVDD/2  VDD/2  0 DC .5,VEq Eq 0 DC 0 PULSE 0 1 5n 0 0 4n,Vsense sense_N 0 DC 0 PULSE 0 1 15n,VsenseP sense_P 0 DC 0 PULSE 1 0 18n,Vra0 ra0 0 dc 0 pulse 0 1.5 12n,Vra1 ra1 0 dc 0,.ic v(bitline0)=250m v(bitline1)=750m V(mb0)=1,.include cmosedu_models.txt,.tran 10p  30n UIC,.options post]
NWire_Pin|pin@25||-11|-3.5||||
Ngeneric:Invisible-Pin|pin@26||-0.75|44.5|||R||ART_message(D5G2;RRR)SPlot Eq, ra0, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
NWire_Pin|pin@27||-16.25|5.75||||
NWire_Pin|pin@28||-11|-14.25||||
NWire_Pin|pin@29||3.25|-14.25||||
NWire_Pin|pin@30||3.25|-3.75||||
NWire_Pin|pin@31||1|13.75||||
NWire_Pin|pin@34||3.25|13.75||||
NWire_Pin|pin@39||-4.5|17.25||||
NWire_Pin|pin@42||-4.5|13.75||||
NWire_Pin|pin@43||-9.5|13.75||||
NWire_Pin|pin@44||-11|13.75||||
NWire_Pin|pin@48||-2.5|13.75||||
NWire_Pin|pin@49||-2.5|16.75||||
NWire_Pin|pin@51||-9.5|20.25||||
NWire_Pin|pin@53||1|20.25||||
NWire_Pin|pin@55||-26|22.25||||
NWire_Pin|pin@56||-21|32.5||||
NWire_Pin|pin@57||13.5|-22||||
NTransistor|pmos@0||-7.5|16.75|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|pmos@1||-1|17.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|pmos@2||-23|22.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NPower|pwr@0||-21|26.5||||
Awire|ACT|D5G1;Y0.75;||1800|pin@51||-9.5|20.25|pin@53||1|20.25
Awire|Eq|D5G1;X-4.75;Y0.75;||1800|pin@27||-16.25|5.75|pin@4||-9|5.75
Awire|NLAT|D5G1;X3.25;Y1;||1800|pin@28||-11|-14.25|pin@1||-3.5|-14.25
Awire|VDD|D5G1;||0|Mbit2|g|-17.75|32.5|pin@56||-21|32.5
Awire|VDD/2|D5G1;X0.25;Y-2.75;||900|pin@3||-3.25|2|pin@5||-3.25|-1.75
Awire|VDD/2|D5G1;||0|nmos@0|g|18.75|-22|pin@57||13.5|-22
Awire|bitline0|D5G1;X-0.25;Y-28.75;||900|pin@11||-11|41.5|pin@44||-11|13.75
Awire|bitline1|D5G1;X0.5;Y-13;||900|pin@34||3.25|13.75|pin@23||3.25|9.75
Awire|mb0|D5G1;||2700|Mbit2|d|-14.75|34.5|Mbit0|s|-14.75|35.5
Awire|net@0|||0|M2|g|0.25|-10|pin@14||-2.75|-10
Awire|net@1|||900|pin@21||3.25|18.25|pin@15||3.25|18
Awire|net@4|||1800|pin@3||-3.25|2|ME2|d|-0.75|2
Awire|net@5|||900|pin@16||21.75|18|Mbit1|d|21.75|-14.75
Awire|net@6|||1800|pin@15||3.25|18|pin@16||21.75|18
Awire|net@7|||1800|M1|g|-8|-10|pin@6||-4.75|-10
Awire|net@8|||2700|ME1|g|-9|5|pin@4||-9|5.75
Awire|net@9|||2700|pin@6||-4.75|-10|pin@7||-4.75|-7.25
Awire|net@10|||2700|M2|d|3.25|-8|pin@8||3.25|-7.25
Awire|net@11|||2700|pin@8||3.25|-7.25|pin@30||3.25|-3.75
Awire|net@12|||2700|pin@14||-2.75|-10|pin@19||-2.75|-6.25
Awire|net@13|||0|pin@19||-2.75|-6.25|pin@20||-11|-6.25
Awire|net@14|||1800|pin@0||-3.5|5.75|pin@12||1.25|5.75
Awire|net@15|||2700|ME1|d|-11|2|pin@22||-11|9.75
Awire|net@16|||0|ME3|d|-5.5|9.75|pin@22||-11|9.75
Awire|net@17|||900|ME3|g|-3.5|6.75|pin@0||-3.5|5.75
Awire|net@18|||0|pin@0||-3.5|5.75|pin@4||-9|5.75
Awire|net@19|||1800|ME1|s|-7|2|pin@3||-3.25|2
Awire|net@20|||2700|M1|d|-11|-8|pin@20||-11|-6.25
Awire|net@21|||0|C_col_array1|a|9.75|-3.75|pin@30||3.25|-3.75
Awire|net@22|||900|pin@12||1.25|5.75|ME2|g|1.25|5
Awire|net@23|||900|ME2|s|3.25|2|pin@30||3.25|-3.75
Awire|net@24|||900|pin@23||3.25|9.75|ME2|s|3.25|2
Awire|net@25|||900|M1|s|-11|-12|pin@28||-11|-14.25
Awire|net@26|||1800|ME3|s|-1.5|9.75|pin@23||3.25|9.75
Awire|net@27|||900|pin@21||3.25|18.25|pin@30||3.25|-3.75
Awire|net@28|||2700|pin@20||-11|-6.25|pin@25||-11|-3.5
Awire|net@29|||1800|pin@7||-4.75|-7.25|pin@8||3.25|-7.25
Awire|net@30|||2700|pin@29||3.25|-14.25|M2|s|3.25|-12
Awire|net@31|||1800|pin@1||-3.5|-14.25|pin@29||3.25|-14.25
Awire|net@32|||2700|MPD|d|-3.5|-15.5|pin@1||-3.5|-14.25
Awire|net@33|||900|gnd@3||9.75|-7.25|C_col_array1|b|9.75|-7.75
Awire|net@34|||900|gnd@2||-17|-7.25|C_col_array0|b|-17|-7.5
Awire|net@35|||2700|pin@25||-11|-3.5|ME1|d|-11|2
Awire|net@36|||1800|C_col_array0|a|-17|-3.5|pin@25||-11|-3.5
Awire|net@37|||2700|Mbit0|d|-14.75|39.5|pin@10||-14.75|41.5
Awire|net@38|||1800|pin@10||-14.75|41.5|pin@11||-11|41.5
Awire|net@39|||2700|gnd@4||-3.5|-19.75|MPD|s|-3.5|-19.5
Awire|net@40|||900|pmos@1|s|1|15.25|pin@31||1|13.75
Awire|net@44|||900|pin@15||3.25|18|pin@34||3.25|13.75
Awire|net@45|||1800|pin@31||1|13.75|pin@34||3.25|13.75
Awire|net@51|||0|pmos@1|g|-2|17.25|pin@39||-4.5|17.25
Awire|net@55|||900|pin@39||-4.5|17.25|pin@42||-4.5|13.75
Awire|net@56|||0|pin@42||-4.5|13.75|pin@43||-9.5|13.75
Awire|net@57|||2700|pin@43||-9.5|13.75|pmos@0|s|-9.5|14.75
Awire|net@58|||2700|pin@22||-11|9.75|pin@44||-11|13.75
Awire|net@59|||0|pin@43||-9.5|13.75|pin@44||-11|13.75
Awire|net@68|||2700|pmos@0|d|-9.5|18.75|pin@51||-9.5|20.25
Awire|net@72|||900|pin@53||1|20.25|pmos@1|d|1|19.25
Awire|net@79|||1800|pmos@0|g|-6.5|16.75|pin@49||-2.5|16.75
Awire|net@81|||900|pin@49||-2.5|16.75|pin@48||-2.5|13.75
Awire|net@82|||0|pin@31||1|13.75|pin@48||-2.5|13.75
Awire|net@85|||900|pwr@0||-21|26.5|pmos@2|d|-21|24.25
Awire|net@86|||1800|pmos@2|s|-21|20.25|pin@51||-9.5|20.25
Awire|net@89|||2700|nmos@0|d|21.75|-20|Mbit1|s|21.75|-18.75
Awire|ra0|D5G1;X2;Y0.75;||0|Mbit0|g|-17.75|37.5|pin@9||-25.5|37.5
Awire|ra1|D5G1;X-1.5;Y0.75;||0|Mbit1|g|18.75|-16.75|pin@13||9.5|-16.75
Awire|sense_N|D5G1;X-7;Y0.75;||0|MPD|g|-6.5|-17.5|pin@2||-15.75|-17.5
Awire|sense_P|D5G1;X-2.75;Y0.25;||0|pmos@2|g|-24|22.25|pin@55||-26|22.25
X

# Cell fig16.27;2{sch}
Cfig16.27;2{sch}||schematic|1181683398593|1182984094156|
NTransistor|M1|D5G1;X1;Y-3;|-16|2.75|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|-5.75|2.75|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS1|D5G1;X1.75;Y-2.75;|-23.75|7|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MS2|D5G1;X1.75;Y-3;|3|7|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MS3|D5G1;X1;Y-3;|-12.5|-4.75|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-10.5|-9||||
NWire_Pin|pin@0||-10.5|-1.5||||
NWire_Pin|pin@1||-9.75|2.75||||
NWire_Pin|pin@2||-11.75|5.5||||
NWire_Pin|pin@3||-3.75|5.5||||
NWire_Pin|pin@4||-9.75|6.5||||
NWire_Pin|pin@6||-18|6.5||||
NWire_Pin|pin@8||-18|-1.5||||
NWire_Pin|pin@9||-3.75|-1.5||||
NWire_Pin|pin@10||-3.75|9||||
NWire_Pin|pin@11||-11.75|2.75||||
Ngeneric:Invisible-Pin|pin@14||-35.75|17.25|||||SIM_spice_card(D5G1;)S[VVDD VDD 0 DC 1,VGND GND 0 DC 0,VCLK CLK 0 DC 0 PULSE 0  1 0 0 0 5n 10n,VIn_P In_P 0 DC 0 PULSE .4 .6 5n 0 0 4n 12n,VIn_N In_N 0 DC 500m,.include cmosedu_models.txt,.tran 10p 30n UIC,.options post]
NWire_Pin|pin@15||-3.75|12||||
NWire_Pin|pin@17||-9.25|15.5||||
NWire_Pin|pin@18||-9.25|12||||
NWire_Pin|pin@19||-18|12||||
NWire_Pin|pin@21||-8.5|12||||
NWire_Pin|pin@22||-8.5|15.25||||
Ngeneric:Invisible-Pin|pin@27||-11|25.25|||||ART_message(D5G1.5;)SPlot clk vin_p+1.25 vin_n+1.25 Out_p+2.5 Out_n+2.5
NWire_Pin|pin@29||-23.75|-4.75||||
NWire_Pin|pin@30||-18|9||||
NWire_Pin|pin@31||-28|-4.75||||
NWire_Pin|pin@38||-31.75|9||||
NWire_Pin|pin@39||10.75|9||||
NWire_Pin|pin@40||-15.75|-4.75||||
NWire_Pin|pin@41||-15.75|-11||||
NWire_Pin|pin@43||3|-11||||
NTransistor|pmos@0||-16|15.25|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|pmos@1||-5.75|15.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NPower|pwr@1||-18|21.25||||
NPower|pwr@2||-3.75|21.5||||
Awire|CLK|D5G1;X-2.5;||0|pin@29||-23.75|-4.75|pin@31||-28|-4.75
Awire|In_N|D5G1;X0.25;Y1;||1800|MS2|s|5|9|pin@39||10.75|9
Awire|In_P|D5G1;X-1.25;Y1;||0|MS1|d|-25.75|9|pin@38||-31.75|9
Awire|Out_N|D5G1;Y0.75;||1800|pin@10||-3.75|9|MS2|d|1|9
Awire|Out_P|D5G1;X-0.5;Y0.75;||1800|MS1|s|-21.75|9|pin@30||-18|9
Awire|net@0|||0|M2|g|-6.75|2.75|pin@1||-9.75|2.75
Awire|net@1|||2700|M2|d|-3.75|4.75|pin@3||-3.75|5.5
Awire|net@2|||1800|pin@0||-10.5|-1.5|pin@9||-3.75|-1.5
Awire|net@3|||2700|MS3|d|-10.5|-2.75|pin@0||-10.5|-1.5
Awire|net@4|||2700|gnd@0||-10.5|-7|MS3|s|-10.5|-6.75
Awire|net@5|||1800|M1|g|-15|2.75|pin@11||-11.75|2.75
Awire|net@6|||2700|pin@11||-11.75|2.75|pin@2||-11.75|5.5
Awire|net@7|||2700|pin@3||-3.75|5.5|pin@10||-3.75|9
Awire|net@8|||2700|pin@1||-9.75|2.75|pin@4||-9.75|6.5
Awire|net@9|||0|pin@4||-9.75|6.5|pin@6||-18|6.5
Awire|net@10|||2700|M1|d|-18|4.75|pin@6||-18|6.5
Awire|net@11|||900|M1|s|-18|0.75|pin@8||-18|-1.5
Awire|net@13|||1800|pin@2||-11.75|5.5|pin@3||-3.75|5.5
Awire|net@14|||2700|pin@9||-3.75|-1.5|M2|s|-3.75|0.75
Awire|net@15|||900|pmos@1|s|-3.75|13.5|pin@15||-3.75|12
Awire|net@17|||0|pmos@1|g|-6.75|15.5|pin@17||-9.25|15.5
Awire|net@18|||900|pin@17||-9.25|15.5|pin@18||-9.25|12
Awire|net@19|||0|pin@18||-9.25|12|pin@19||-18|12
Awire|net@20|||2700|pin@19||-18|12|pmos@0|s|-18|13.25
Awire|net@25|||1800|pmos@0|g|-15|15.25|pin@22||-8.5|15.25
Awire|net@26|||900|pin@22||-8.5|15.25|pin@21||-8.5|12
Awire|net@27|||0|pin@15||-3.75|12|pin@21||-8.5|12
Awire|net@30|||2700|pin@10||-3.75|9|pin@15||-3.75|12
Awire|net@39|||2700|pin@29||-23.75|-4.75|MS1|g|-23.75|6
Awire|net@44|||900|pin@30||-18|9|pin@6||-18|6.5
Awire|net@45|||900|pin@19||-18|12|pin@30||-18|9
Awire|net@56|||2700|pmos@0|d|-18|17.25|pwr@1||-18|21.25
Awire|net@58|||900|pwr@2||-3.75|21.5|pmos@1|d|-3.75|17.5
Awire|net@63|||0|pin@40||-15.75|-4.75|pin@29||-23.75|-4.75
Awire|net@64|||0|MS3|g|-13.5|-4.75|pin@40||-15.75|-4.75
Awire|net@65|||900|pin@40||-15.75|-4.75|pin@41||-15.75|-11
Awire|net@69|||1800|pin@41||-15.75|-11|pin@43||3|-11
Awire|net@70|||900|MS2|g|3|6|pin@43||3|-11
Awire|net@71|||1800|pin@8||-18|-1.5|pin@0||-10.5|-1.5
X

# Cell fig16.28;1{sch}
Cfig16.28;1{sch}||schematic|1181684539890|1208961236421|
NTransistor|M1|D5G1;X1;Y-3;|-8.75|-4|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|1.5|-4|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M3|D5G1;X0.75;Y-3.25;|-27.5|5.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G1;X-0.75;Y-3;)SP_50n
NTransistor|M4|D5G1;X1;Y-3;|-27.5|-2.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X-1;Y-3.25;)SN_50n
NTransistor|M5|D5G1;X0.75;Y-3.25;|22.25|5.5|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G1;X-0.75;Y-3;)SP_50n
NTransistor|M6|D5G1;X1;Y-3;|22.25|-1.5|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X-1;Y-3.25;)SN_50n
NTransistor|MS1|D5G1;X1.75;Y-2.75;|-16.5|0.25|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MS2|D5G1;X1.75;Y-3;|10.25|0.25|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MS3|D5G1;X1;Y-3;|-5.25|-11.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-3.25|-15.75||||
NGround|gnd@1||-25.5|-8.25||||
NGround|gnd@2||20.25|-7.5||||
NGround|gnd@3||28|-2.25||||
NWire_Pin|pin@0||-3.25|-8.25||||
NWire_Pin|pin@1||-2.5|-4||||
NWire_Pin|pin@2||3.5|2.25||||
NWire_Pin|pin@3||-4.5|-4||||
Ngeneric:Invisible-Pin|pin@4||-24.25|15.25|||||SIM_spice_card(D5G1;)S[VVDD VDD 0 DC 1,VGND GND 0 DC 0,VCLK CLK 0 DC 0 PULSE 0  1 0 10p 10p  5n 10n,.include cmosedu_models.txt,.tran 1p 21n 19n 10p uic,.options post]
NWire_Pin|pin@5||3.5|5.25||||
NWire_Pin|pin@6||-2|8.75||||
NWire_Pin|pin@7||-2|5.25||||
NWire_Pin|pin@8||-10.75|5.25||||
NWire_Pin|pin@9||-4.5|-1.25||||
NWire_Pin|pin@10||-1.25|5.25||||
NWire_Pin|pin@11||-1.25|8.5||||
Ngeneric:Invisible-Pin|pin@12||-3.5|17.5|||||ART_message(D5G1.5;)SPlot in_p and then in_n
NWire_Pin|pin@13||-16.5|-11.5||||
NWire_Pin|pin@14||3.5|-1.25||||
NWire_Pin|pin@15||-10.75|2.25||||
NWire_Pin|pin@16||-20.75|-11.5||||
NWire_Pin|pin@19||-2.5|-0.25||||
NWire_Pin|pin@23||-10.75|-0.25||||
NWire_Pin|pin@24||-10.75|-8.25||||
NWire_Pin|pin@25||3.5|-8.25||||
NWire_Pin|pin@26||10.25|-11.5||||
NWire_Pin|pin@28||-31|1.75||||
NWire_Pin|pin@30||-31|5.25||||
NWire_Pin|pin@31||-31|-2.5||||
NWire_Pin|pin@34||24|-1.5||||
NWire_Pin|pin@35||24|5.5||||
NWire_Pin|pin@39||24|2.25||||
NWire_Pin|pin@41||-25.5|2.25||||
NWire_Pin|pin@42||20.25|2.25||||
NWire_Pin|pin@43||-35.25|1.75||||
NWire_Pin|pin@44||28|2.25||||
NTransistor|pmos@0||-8.75|8.5|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|pmos@1||1.5|8.75|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NPower|pwr@0||-10.75|14.5||||
NPower|pwr@1||3.5|14.75||||
NPower|pwr@2||-25.5|10||||
NPower|pwr@3||20.25|10.75||||
NPower|pwr@4||-35.25|9.75||||
Awire|CLK|D5G1;X-2.5;||0|pin@13||-16.5|-11.5|pin@16||-20.75|-11.5
Awire|In_N|D5G1;X0.25;Y1;||1800|MS2|s|12.25|2.25|pin@42||20.25|2.25
Awire|In_P|D5G1;X0.25;Y1;||0|MS1|d|-18.5|2.25|pin@41||-25.5|2.25
Awire|Out_N|D5G1;Y0.75;||1800|pin@2||3.5|2.25|MS2|d|8.25|2.25
Awire|Out_P|D5G1;X-0.5;Y0.75;||1800|MS1|s|-14.5|2.25|pin@15||-10.75|2.25
Awire|net@0|||0|M2|g|0.5|-4|pin@1||-2.5|-4
Awire|net@1|||2700|M2|d|3.5|-2|pin@14||3.5|-1.25
Awire|net@2|||2700|M1|d|-10.75|-2|pin@23||-10.75|-0.25
Awire|net@3|||900|M1|s|-10.75|-6|pin@24||-10.75|-8.25
Awire|net@4|||1800|pin@9||-4.5|-1.25|pin@14||3.5|-1.25
Awire|net@5|||2700|pin@25||3.5|-8.25|M2|s|3.5|-6
Awire|net@6|||900|pmos@1|s|3.5|6.75|pin@5||3.5|5.25
Awire|net@7|||0|pmos@1|g|0.5|8.75|pin@6||-2|8.75
Awire|net@8|||900|pin@6||-2|8.75|pin@7||-2|5.25
Awire|net@9|||0|pin@7||-2|5.25|pin@8||-10.75|5.25
Awire|net@10|||1800|pin@0||-3.25|-8.25|pin@25||3.5|-8.25
Awire|net@11|||2700|pin@8||-10.75|5.25|pmos@0|s|-10.75|6.5
Awire|net@12|||1800|pmos@0|g|-7.75|8.5|pin@11||-1.25|8.5
Awire|net@13|||900|pin@11||-1.25|8.5|pin@10||-1.25|5.25
Awire|net@14|||0|pin@5||3.5|5.25|pin@10||-1.25|5.25
Awire|net@15|||2700|MS3|d|-3.25|-9.5|pin@0||-3.25|-8.25
Awire|net@16|||2700|pin@2||3.5|2.25|pin@5||3.5|5.25
Awire|net@17|||2700|pin@13||-16.5|-11.5|MS1|g|-16.5|-0.75
Awire|net@18|||2700|gnd@0||-3.25|-13.75|MS3|s|-3.25|-13.5
Awire|net@19|||900|pin@15||-10.75|2.25|pin@23||-10.75|-0.25
Awire|net@20|||900|pin@8||-10.75|5.25|pin@15||-10.75|2.25
Awire|net@21|||1800|M1|g|-7.75|-4|pin@3||-4.5|-4
Awire|net@22|||2700|pmos@0|d|-10.75|10.5|pwr@0||-10.75|14.5
Awire|net@23|||900|pwr@1||3.5|14.75|pmos@1|d|3.5|10.75
Awire|net@24|||2700|pin@3||-4.5|-4|pin@9||-4.5|-1.25
Awire|net@28|||2700|pin@14||3.5|-1.25|pin@2||3.5|2.25
Awire|net@30|||1800|pin@24||-10.75|-8.25|pin@0||-3.25|-8.25
Awire|net@31|||2700|pin@1||-2.5|-4|pin@19||-2.5|-0.25
Awire|net@32|||0|pin@19||-2.5|-0.25|pin@23||-10.75|-0.25
Awire|net@33|||1800|pin@13||-16.5|-11.5|MS3|g|-6.25|-11.5
Awire|net@34|||900|MS2|g|10.25|-0.75|pin@26||10.25|-11.5
Awire|net@37|||1800|pin@31||-31|-2.5|M4|g|-28.5|-2.5
Awire|net@39|||2700|M3|d|-25.5|7.25|pwr@2||-25.5|10
Awire|net@40|||2700|gnd@1||-25.5|-6.25|M4|s|-25.5|-4.5
Awire|net@41|||0|M3|g|-28.5|5.25|pin@30||-31|5.25
Awire|net@42|||900|pin@28||-31|1.75|pin@31||-31|-2.5
Awire|net@44|||900|pin@30||-31|5.25|pin@28||-31|1.75
Awire|net@47|||2700|M4|d|-25.5|-0.5|pin@41||-25.5|2.25
Awire|net@48|||1800|M6|g|23.25|-1.5|pin@34||24|-1.5
Awire|net@49|||0|pin@35||24|5.5|M5|g|23.25|5.5
Awire|net@50|||2700|gnd@2||20.25|-5.5|M6|s|20.25|-3.5
Awire|net@56|||2700|pin@34||24|-1.5|pin@39||24|2.25
Awire|net@57|||2700|pin@39||24|2.25|pin@35||24|5.5
Awire|net@59|||2700|M6|d|20.25|0.5|pin@42||20.25|2.25
Awire|net@60|||2700|pin@41||-25.5|2.25|M3|s|-25.5|3.25
Awire|net@62|||2700|pin@42||20.25|2.25|M5|s|20.25|3.5
Awire|net@65|||2700|pin@43||-35.25|1.75|pwr@4||-35.25|9.75
Awire|net@66|||2700|gnd@3||28|-0.25|pin@44||28|2.25
Awire|net@68|||0|pin@26||10.25|-11.5|MS3|g|-6.25|-11.5
Awire|net@69|||0|pin@28||-31|1.75|pin@43||-35.25|1.75
Awire|net@70|||2700|M5|d|20.25|7.5|pwr@3||20.25|10.75
Awire|net@71|||1800|pin@39||24|2.25|pin@44||28|2.25
X

# Cell fig16.29;1{sch}
Cfig16.29;1{sch}||schematic|1181685041000|1208961243968|
NTransistor|M1|D5G1;X1;Y-3;|-14.5|-9.5|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|-4.25|-9.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS1|D5G1;X1.75;Y-2.75;|-22.25|-5.25|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MS2|D5G1;X1.75;Y-3;|4.5|-5.25|||RR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MS3|D5G1;X1;Y-3;|-11|-17|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-9|-21.25||||
NWire_Pin|pin@0||-9|-13.75||||
NWire_Pin|pin@1||-8.25|-9.5||||
NWire_Pin|pin@2||-2.25|-3.25||||
NWire_Pin|pin@3||-10.25|-9.5||||
Ngeneric:Invisible-Pin|pin@4||-31|5|||||SIM_spice_card(D5G1;)S[VVDD VDD 0 DC 1,VGND GND 0 DC 0,VCLK CLK 0 DC 0 PULSE 0  1 0 0 0 5n 10n,VIn_P In_P 0 DC 0 PULSE .4 .6 5n 0 0 4n 12n,VIn_N In_N 0 DC 500m,.include cmosedu_models.txt,.tran 10p 31n 1n uic,.options post]
NWire_Pin|pin@5||-2.25|-0.25||||
NWire_Pin|pin@6||-7.75|3.25||||
NWire_Pin|pin@7||-7.75|-0.25||||
NWire_Pin|pin@8||-16.5|-0.25||||
NWire_Pin|pin@9||-10.25|-6.75||||
NWire_Pin|pin@10||-7|-0.25||||
NWire_Pin|pin@11||-7|3||||
Ngeneric:Invisible-Pin|pin@12||-9|11.75|||||ART_message(D5G1.5;)SPlot -I(VDD)
NWire_Pin|pin@13||-22.25|-17||||
NWire_Pin|pin@14||-2.25|-6.75||||
NWire_Pin|pin@15||-16.5|-3.25||||
NWire_Pin|pin@16||-26.5|-17||||
NWire_Pin|pin@17||-30.25|-3.25||||
NWire_Pin|pin@18||12.25|-3.25||||
NWire_Pin|pin@19||-8.25|-5.75||||
NWire_Pin|pin@20||-14.25|-17||||
NWire_Pin|pin@22||4.5|-17||||
NWire_Pin|pin@23||-16.5|-5.75||||
NWire_Pin|pin@24||-16.5|-13.75||||
NWire_Pin|pin@25||-2.25|-13.75||||
NTransistor|pmos@0||-14.5|3|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|pmos@1||-4.25|3.25|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NPower|pwr@0||-16.5|9||||
NPower|pwr@1||-2.25|9.25||||
Awire|CLK|D5G1;X-2.5;||0|pin@13||-22.25|-17|pin@16||-26.5|-17
Awire|In_N|D5G1;X0.25;Y1;||1800|MS2|s|6.5|-3.25|pin@18||12.25|-3.25
Awire|In_P|D5G1;X-1.25;Y1;||0|MS1|d|-24.25|-3.25|pin@17||-30.25|-3.25
Awire|Out_N|D5G1;Y0.75;||1800|pin@2||-2.25|-3.25|MS2|d|2.5|-3.25
Awire|Out_P|D5G1;X-0.5;Y0.75;||1800|MS1|s|-20.25|-3.25|pin@15||-16.5|-3.25
Awire|net@0|||2700|pin@2||-2.25|-3.25|pin@5||-2.25|-0.25
Awire|net@1|||2700|pin@13||-22.25|-17|MS1|g|-22.25|-6.25
Awire|net@2|||2700|gnd@0||-9|-19.25|MS3|s|-9|-19
Awire|net@3|||900|pin@15||-16.5|-3.25|pin@23||-16.5|-5.75
Awire|net@4|||900|pin@8||-16.5|-0.25|pin@15||-16.5|-3.25
Awire|net@5|||1800|M1|g|-13.5|-9.5|pin@3||-10.25|-9.5
Awire|net@6|||2700|pmos@0|d|-16.5|5|pwr@0||-16.5|9
Awire|net@7|||900|pwr@1||-2.25|9.25|pmos@1|d|-2.25|5.25
Awire|net@8|||2700|pin@3||-10.25|-9.5|pin@9||-10.25|-6.75
Awire|net@9|||0|pin@20||-14.25|-17|pin@13||-22.25|-17
Awire|net@10|||0|MS3|g|-12|-17|pin@20||-14.25|-17
Awire|net@12|||2700|pin@14||-2.25|-6.75|pin@2||-2.25|-3.25
Awire|net@13|||900|MS2|g|4.5|-6.25|pin@22||4.5|-17
Awire|net@14|||1800|pin@24||-16.5|-13.75|pin@0||-9|-13.75
Awire|net@15|||2700|pin@1||-8.25|-9.5|pin@19||-8.25|-5.75
Awire|net@16|||0|pin@19||-8.25|-5.75|pin@23||-16.5|-5.75
Awire|net@17|||0|M2|g|-5.25|-9.5|pin@1||-8.25|-9.5
Awire|net@18|||2700|M2|d|-2.25|-7.5|pin@14||-2.25|-6.75
Awire|net@19|||2700|M1|d|-16.5|-7.5|pin@23||-16.5|-5.75
Awire|net@20|||900|M1|s|-16.5|-11.5|pin@24||-16.5|-13.75
Awire|net@21|||1800|pin@9||-10.25|-6.75|pin@14||-2.25|-6.75
Awire|net@22|||2700|pin@25||-2.25|-13.75|M2|s|-2.25|-11.5
Awire|net@23|||900|pmos@1|s|-2.25|1.25|pin@5||-2.25|-0.25
Awire|net@24|||0|pmos@1|g|-5.25|3.25|pin@6||-7.75|3.25
Awire|net@25|||900|pin@6||-7.75|3.25|pin@7||-7.75|-0.25
Awire|net@26|||0|pin@7||-7.75|-0.25|pin@8||-16.5|-0.25
Awire|net@27|||1800|pin@0||-9|-13.75|pin@25||-2.25|-13.75
Awire|net@28|||2700|pin@8||-16.5|-0.25|pmos@0|s|-16.5|1
Awire|net@29|||1800|pmos@0|g|-13.5|3|pin@11||-7|3
Awire|net@30|||900|pin@11||-7|3|pin@10||-7|-0.25
Awire|net@31|||0|pin@5||-2.25|-0.25|pin@10||-7|-0.25
Awire|net@32|||2700|MS3|d|-9|-15|pin@0||-9|-13.75
Awire|net@34|||1800|pin@20||-14.25|-17|pin@22||4.5|-17
X

# Cell fig16.36;1{sch}
Cfig16.36;1{sch}||schematic|1181685254843|1183054891750|
NTransistor|M1|D5G1;X1;Y-3;|-16.5|-7.75|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|-5.75|-7.75|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M3|D5G1;X1.75;Y-2.75;|-16.5|12.5|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|M4|D5G1;X2;Y-2.75;|-5.75|12.75|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MB1|D5G1;X1;Y-3;|-20.5|-13.25|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MB2|D5G1;X1;Y-3;|-1.75|-13|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS1|D5G1;X1;Y-3;|-20.5|3.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS2|D5G1;X1;Y-3;|-5.75|3.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS3|D5G1;X1.75;Y-2.75;|-27.5|12.75|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MS4|D5G1;X1.75;Y-3;|4.75|13.25|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
INAND;1{ic}|NAND@0||13.5|1.5|||D5G4;
INAND;1{ic}|NAND@1||13.5|-10.5|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@1||-18.5|-18.75||||
NGround|gnd@2||-3.75|-19||||
NWire_Pin|pin@1||-10.25|-7.75||||
NWire_Pin|pin@2||-9.25|9.25||||
NWire_Pin|pin@3||-9.25|12.5||||
NWire_Pin|pin@5||-3.75|7||||
NWire_Pin|pin@7||-10.25|6.5||||
NWire_Pin|pin@9||-18.5|6.5||||
NWire_Pin|pin@13||-12.25|-7.75||||
NWire_Pin|pin@14||-3.75|9.25||||
NWire_Pin|pin@15||-10|12.75||||
NWire_Pin|pin@16||-10|9||||
NWire_Pin|pin@17||-18.5|9||||
NWire_Pin|pin@18||-12.25|7||||
NWire_Pin|pin@22||-29|-13.25||||
NWire_Pin|pin@23||7|-13||||
NWire_Pin|pin@26||-30|12.75||||
NWire_Pin|pin@27||-30|3.5||||
NWire_Pin|pin@28||-25.5|9||||
NWire_Pin|pin@29||-28.25|9||||
NWire_Pin|pin@30||8.25|9.25||||
NWire_Pin|pin@33||2.75|9.25||||
NWire_Pin|pin@34||6.25|3.5||||
NWire_Pin|pin@35||6.25|13.25||||
NWire_Pin|pin@36||-33.25|3.5||||
NWire_Pin|pin@37||8.25|1.75||||
NWire_Pin|pin@38||8.5|-8||||
NWire_Pin|pin@39||8.5|-4||||
NWire_Pin|pin@41||21.25|2.75||||
NWire_Pin|pin@42||21.25|-4||||
NWire_Pin|pin@45||-28.25|-10.25||||
NWire_Pin|pin@46||8.25|-2||||
NWire_Pin|pin@47||23.75|2.75||||
NWire_Pin|pin@48||24|-9.25||||
NWire_Pin|pin@50||21.75|-2||||
NWire_Pin|pin@51||21.75|-9.25||||
NWire_Pin|pin@53||8.25|4||||
Ngeneric:Invisible-Pin|pin@54||20|15.75|||||SIM_spice_card(D5G1;)S[VVDD VDD 0 DC 1,VGND GND 0 DC 0,VCLK CLK 0 DC 0 PULSE 0  1 0 0 0 5n 10n,VInP InP 0 DC 0 PULSE .4 .6 5n 0 0 4n 12n,VInN InN 0 DC 500m,.include cmosedu_models.txt,.tran 10p 31n 1n uic,.options post]
Ngeneric:Invisible-Pin|pin@55||-11.25|21.5|||||ART_message(D5G2;)SPlot -I(VDD)
NPower|pwr@0||-18.5|18.5||||
NPower|pwr@1||-3.75|18.75||||
NPower|pwr@2||-25.5|18.5||||
NPower|pwr@3||2.75|18.5||||
Awire|CLK|D5G1.5;X-0.25;Y0.75;||1800|pin@36||-33.25|3.5|pin@27||-30|3.5
Awire|InN|D5G1.5;Y0.75;||1800|MB2|g|-0.75|-13|pin@23||7|-13
Awire|InP|D5G1.5;X-3.5;Y0.75;||0|MB1|g|-21.5|-13.25|pin@22||-29|-13.25
Awire|OutN|D5G1.5;X35.75;Y-18.75;||0|pin@28||-25.5|9|pin@29||-28.25|9
Awire|OutP|D5G1.5;X4;Y-4.5;||0|pin@30||8.25|9.25|pin@33||2.75|9.25
Awire|Q|D5G1.5;X1.5;Y0.25;||1800|pin@51||21.75|-9.25|pin@48||24|-9.25
Awire|Qbar|D5G1.5;X1.75;Y0.25;||1800|pin@41||21.25|2.75|pin@47||23.75|2.75
Awire|net@0|||0|M2|g|-6.75|-7.75|pin@1||-10.25|-7.75
Awire|net@3|||2700|pin@17||-18.5|9|M3|s|-18.5|10.5
Awire|net@4|||1800|M3|g|-15.5|12.5|pin@3||-9.25|12.5
Awire|net@5|||900|pin@3||-9.25|12.5|pin@2||-9.25|9.25
Awire|net@6|||0|pin@14||-3.75|9.25|pin@2||-9.25|9.25
Awire|net@13|||1800|M1|g|-15.5|-7.75|pin@13||-12.25|-7.75
Awire|net@14|||2700|M3|d|-18.5|14.5|pwr@0||-18.5|18.5
Awire|net@15|||900|pwr@1||-3.75|18.75|M4|d|-3.75|14.75
Awire|net@16|||2700|pin@13||-12.25|-7.75|pin@18||-12.25|7
Awire|net@20|||2700|pin@1||-10.25|-7.75|pin@7||-10.25|6.5
Awire|net@21|||0|pin@7||-10.25|6.5|pin@9||-18.5|6.5
Awire|net@23|||1800|pin@18||-12.25|7|pin@5||-3.75|7
Awire|net@25|||900|M4|s|-3.75|10.75|pin@14||-3.75|9.25
Awire|net@27|||0|M4|g|-6.75|12.75|pin@15||-10|12.75
Awire|net@28|||900|pin@15||-10|12.75|pin@16||-10|9
Awire|net@29|||0|pin@16||-10|9|pin@17||-18.5|9
Awire|net@31|||2700|pin@9||-18.5|6.5|pin@17||-18.5|9
Awire|net@32|||900|pin@14||-3.75|9.25|pin@5||-3.75|7
Awire|net@42|||2700|gnd@1||-18.5|-16.75|MB1|s|-18.5|-15.25
Awire|net@43|||2700|gnd@2||-3.75|-17|MB2|s|-3.75|-15
Awire|net@46|||2700|MB2|d|-3.75|-11|M2|s|-3.75|-9.75
Awire|net@47|||2700|MS2|d|-3.75|5.5|pin@5||-3.75|7
Awire|net@48|||0|MS2|g|-6.75|3.5|MS1|g|-21.5|3.5
Awire|net@49|||900|MS2|s|-3.75|1.5|M2|d|-3.75|-5.75
Awire|net@50|||2700|M1|d|-18.5|-5.75|MS1|s|-18.5|1.5
Awire|net@51|||2700|MS1|d|-18.5|5.5|pin@9||-18.5|6.5
Awire|net@52|||0|MS1|g|-21.5|3.5|pin@27||-30|3.5
Awire|net@53|||0|MS3|g|-28.5|12.75|pin@26||-30|12.75
Awire|net@55|||900|pin@26||-30|12.75|pin@27||-30|3.5
Awire|net@56|||0|pin@17||-18.5|9|pin@28||-25.5|9
Awire|net@58|||2700|pin@28||-25.5|9|MS3|s|-25.5|10.75
Awire|net@63|||2700|MS3|d|-25.5|14.75|pwr@2||-25.5|18.5
Awire|net@67|||0|pin@33||2.75|9.25|pin@14||-3.75|9.25
Awire|net@68|||900|MS4|s|2.75|11.25|pin@33||2.75|9.25
Awire|net@69|||1800|MS2|g|-6.75|3.5|pin@34||6.25|3.5
Awire|net@70|||2700|pin@34||6.25|3.5|pin@35||6.25|13.25
Awire|net@71|||1800|MS4|g|5.75|13.25|pin@35||6.25|13.25
Awire|net@73|||0|NAND@0|B|10.25|1.75|pin@37||8.25|1.75
Awire|net@74|||0|NAND@1|A|10.25|-8|pin@38||8.5|-8
Awire|net@75|||2700|pin@38||8.5|-8|pin@39||8.5|-4
Awire|net@77|||1800|NAND@0|Out|18.5|2.75|pin@41||21.25|2.75
Awire|net@78|||900|pin@41||21.25|2.75|pin@42||21.25|-4
Awire|net@82|||900|pin@29||-28.25|9|pin@45||-28.25|-10.25
Awire|net@89|||1800|NAND@1|Out|18.5|-9.25|pin@51||21.75|-9.25
Awire|net@90|||900|pin@50||21.75|-2|pin@51||21.75|-9.25
Awire|net@91|||900|pin@37||8.25|1.75|pin@46||8.25|-2
Awire|net@92|||1800|pin@46||8.25|-2|pin@50||21.75|-2
Awire|net@95|||2700|pin@53||8.25|4|pin@30||8.25|9.25
Awire|net@96|||1800|pin@53||8.25|4|NAND@0|A|10.25|4
Awire|net@99|||0|pin@42||21.25|-4|pin@39||8.5|-4
Awire|net@100|||0|NAND@1|B|10.25|-10.25|pin@45||-28.25|-10.25
Awire|net@101|||2700|MB1|d|-18.5|-11.25|M1|s|-18.5|-9.75
Awire|net@102|||2700|MS4|d|2.75|15.25|pwr@3||2.75|18.5
X

# Cell fig16.37;1{sch}
Cfig16.37;1{sch}||schematic|1181687084671|1182984135531|
NTransistor|M1|D5G1;X1;Y-3;|-21.25|-12.5|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|-10.5|-12.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M3|D5G1;X1.75;Y-2.75;|-21.25|7.75|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|M4|D5G1;X2;Y-2.75;|-10.5|8|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|M5|D5G1;X0.75;Y-3.25;|-39.25|-23|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G1;X-0.75;Y-3;)SP_50n
NTransistor|M6|D5G1;X1;Y-3;|-39.25|-30.75|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X-1;Y-3.25;)SN_50n
NTransistor|M7|D5G1;X0.75;Y-3.25;|6.25|-23.75|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G1;X-0.75;Y-3;)SP_50n
NTransistor|M8|D5G1;X1;Y-3;|6.25|-30.75|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D20.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X-1;Y-3.25;)SN_50n
NTransistor|MB1|D5G1;X1;Y-3;|-25.25|-27|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MB2|D5G1;X1;Y-3;|-6.5|-27.25|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS1|D5G1;X1;Y-3;|-25.25|-1.25|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS2|D5G1;X1;Y-3;|-10.5|-1.25|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS3|D5G1;X1.75;Y-2.75;|-32.25|8|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MS4|D5G1;X1.75;Y-3;|0|8.5|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
INAND;1{ic}|NAND@0||8.75|-3.25|||D5G4;
INAND;1{ic}|NAND@1||8.75|-15.25|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-23.25|-33.75||||
NGround|gnd@1||-8.5|-34.25||||
NGround|gnd@2||-37.25|-36.5||||
NGround|gnd@3||4.25|-36.75||||
NGround|gnd@4||12|-31.5||||
NWire_Pin|pin@0||-15|-12.5||||
NWire_Pin|pin@1||-17|-12.5||||
NWire_Pin|pin@2||-8.5|4.5||||
NWire_Pin|pin@3||-14.75|8||||
NWire_Pin|pin@4||-14.75|4.25||||
NWire_Pin|pin@5||-23.25|4.25||||
NWire_Pin|pin@6||-17|2.25||||
NWire_Pin|pin@7||-14|4.5||||
NWire_Pin|pin@10||-34.75|8||||
NWire_Pin|pin@11||-34.75|-1.25||||
NWire_Pin|pin@12||-30.25|4.25||||
NWire_Pin|pin@13||-33|4.25||||
NWire_Pin|pin@14||-14|7.75||||
NWire_Pin|pin@15||3.5|4.5||||
NWire_Pin|pin@16||-2|4.5||||
NWire_Pin|pin@17||1.5|-1.25||||
NWire_Pin|pin@18||1.5|8.5||||
NWire_Pin|pin@19||-38|-1.25||||
NWire_Pin|pin@20||3.5|-3||||
NWire_Pin|pin@21||3.75|-12.75||||
NWire_Pin|pin@22||3.75|-8.75||||
NWire_Pin|pin@23||16.5|-2||||
NWire_Pin|pin@24||16.5|-8.75||||
NWire_Pin|pin@25||-33|-15||||
NWire_Pin|pin@26||3.5|-6.75||||
NWire_Pin|pin@27||19|-2||||
NWire_Pin|pin@28||19.25|-14||||
NWire_Pin|pin@29||-8.5|2.25||||
NWire_Pin|pin@30||17|-6.75||||
NWire_Pin|pin@31||17|-14||||
NWire_Pin|pin@32||3.5|-0.75||||
Ngeneric:Invisible-Pin|pin@33||15|11.75|||||SIM_spice_card(D5G1;)S[VVDD VDD 0 DC 1,VGND GND 0 DC 0,VCLK CLK 0 DC 0 PULSE 0  1 0 0 0 5n 10n,.include cmosedu_models.txt,.tran 1p 21n 19n uic,.options post]
Ngeneric:Invisible-Pin|pin@34||-15|18.25|||||ART_message(D5G2;)SPlot InP and then InN
NWire_Pin|pin@35||-15|1.75||||
NWire_Pin|pin@36||-23.25|1.75||||
NWire_Pin|pin@37||-42.75|-26.5||||
NWire_Pin|pin@38||-42.75|-23||||
NWire_Pin|pin@39||-42.75|-30.75||||
NWire_Pin|pin@41||-47|-26.5||||
NWire_Pin|pin@42||8|-30.75||||
NWire_Pin|pin@43||8|-23.75||||
NWire_Pin|pin@44||8|-27||||
NWire_Pin|pin@46||12|-27||||
NWire_Pin|pin@47||-37.25|-27||||
NWire_Pin|pin@48||4.25|-27.25||||
NPower|pwr@0||-23.25|13.75||||
NPower|pwr@1||-8.5|14||||
NPower|pwr@2||-30.25|13.75||||
NPower|pwr@3||-2|13.75||||
NPower|pwr@4||-37.25|-18.25||||
NPower|pwr@5||-47|-18.5||||
NPower|pwr@6||4.25|-18.5||||
Awire|CLK|D5G1.5;X-3.25;Y0.25;||1800|pin@19||-38|-1.25|pin@11||-34.75|-1.25
Awire|InN|D5G1.5;X-1.5;Y1.5;||1800|MB2|g|-5.5|-27.25|pin@48||4.25|-27.25
Awire|InP|D5G1.5;X1.5;Y1.5;||0|MB1|g|-26.25|-27|pin@47||-37.25|-27
Awire|OutN|D5G1.5;X31.5;Y-18.75;||0|pin@12||-30.25|4.25|pin@13||-33|4.25
Awire|OutP|D5G1.5;X4.25;Y-2.5;||0|pin@15||3.5|4.5|pin@16||-2|4.5
Awire|Q|D5G1.5;X3;Y0.25;||1800|pin@31||17|-14|pin@28||19.25|-14
Awire|Qbar|D5G1.5;X4;Y0.25;||1800|pin@23||16.5|-2|pin@27||19|-2
Awire|net@0|||0|M2|g|-11.5|-12.5|pin@0||-15|-12.5
Awire|net@1|||0|NAND@1|B|5.5|-15|pin@25||-33|-15
Awire|net@2|||2700|MB1|d|-23.25|-25|M1|s|-23.25|-14.5
Awire|net@3|||2700|MS4|d|-2|10.5|pwr@3||-2|13.75
Awire|net@4|||1800|M1|g|-20.25|-12.5|pin@1||-17|-12.5
Awire|net@5|||2700|M3|d|-23.25|9.75|pwr@0||-23.25|13.75
Awire|net@6|||900|pwr@1||-8.5|14|M4|d|-8.5|10
Awire|net@7|||2700|pin@1||-17|-12.5|pin@6||-17|2.25
Awire|net@8|||2700|pin@0||-15|-12.5|pin@35||-15|1.75
Awire|net@9|||0|pin@35||-15|1.75|pin@36||-23.25|1.75
Awire|net@10|||1800|pin@6||-17|2.25|pin@29||-8.5|2.25
Awire|net@11|||900|M4|s|-8.5|6|pin@2||-8.5|4.5
Awire|net@12|||0|M4|g|-11.5|8|pin@3||-14.75|8
Awire|net@13|||900|pin@3||-14.75|8|pin@4||-14.75|4.25
Awire|net@14|||0|pin@4||-14.75|4.25|pin@5||-23.25|4.25
Awire|net@15|||2700|pin@5||-23.25|4.25|M3|s|-23.25|5.75
Awire|net@16|||2700|pin@36||-23.25|1.75|pin@5||-23.25|4.25
Awire|net@17|||900|pin@2||-8.5|4.5|pin@29||-8.5|2.25
Awire|net@18|||1800|M3|g|-20.25|7.75|pin@14||-14|7.75
Awire|net@19|||2700|gnd@0||-23.25|-31.75|MB1|s|-23.25|-29
Awire|net@20|||2700|gnd@1||-8.5|-32.25|MB2|s|-8.5|-29.25
Awire|net@21|||2700|MB2|d|-8.5|-25.25|M2|s|-8.5|-14.5
Awire|net@22|||2700|MS2|d|-8.5|0.75|pin@29||-8.5|2.25
Awire|net@23|||0|MS2|g|-11.5|-1.25|MS1|g|-26.25|-1.25
Awire|net@24|||900|MS2|s|-8.5|-3.25|M2|d|-8.5|-10.5
Awire|net@25|||900|pin@14||-14|7.75|pin@7||-14|4.5
Awire|net@26|||2700|M1|d|-23.25|-10.5|MS1|s|-23.25|-3.25
Awire|net@27|||2700|MS1|d|-23.25|0.75|pin@36||-23.25|1.75
Awire|net@28|||0|MS1|g|-26.25|-1.25|pin@11||-34.75|-1.25
Awire|net@29|||0|MS3|g|-33.25|8|pin@10||-34.75|8
Awire|net@30|||900|pin@10||-34.75|8|pin@11||-34.75|-1.25
Awire|net@31|||0|pin@5||-23.25|4.25|pin@12||-30.25|4.25
Awire|net@32|||2700|pin@12||-30.25|4.25|MS3|s|-30.25|6
Awire|net@33|||0|pin@2||-8.5|4.5|pin@7||-14|4.5
Awire|net@34|||2700|MS3|d|-30.25|10|pwr@2||-30.25|13.75
Awire|net@35|||0|pin@16||-2|4.5|pin@2||-8.5|4.5
Awire|net@36|||900|MS4|s|-2|6.5|pin@16||-2|4.5
Awire|net@37|||1800|MS2|g|-11.5|-1.25|pin@17||1.5|-1.25
Awire|net@38|||2700|pin@17||1.5|-1.25|pin@18||1.5|8.5
Awire|net@39|||1800|MS4|g|1|8.5|pin@18||1.5|8.5
Awire|net@40|||0|NAND@0|B|5.5|-3|pin@20||3.5|-3
Awire|net@41|||0|NAND@1|A|5.5|-12.75|pin@21||3.75|-12.75
Awire|net@42|||2700|pin@21||3.75|-12.75|pin@22||3.75|-8.75
Awire|net@43|||1800|NAND@0|Out|13.75|-2|pin@23||16.5|-2
Awire|net@44|||900|pin@23||16.5|-2|pin@24||16.5|-8.75
Awire|net@45|||900|pin@13||-33|4.25|pin@25||-33|-15
Awire|net@46|||1800|NAND@1|Out|13.75|-14|pin@31||17|-14
Awire|net@47|||900|pin@30||17|-6.75|pin@31||17|-14
Awire|net@48|||900|pin@20||3.5|-3|pin@26||3.5|-6.75
Awire|net@49|||1800|pin@26||3.5|-6.75|pin@30||17|-6.75
Awire|net@50|||2700|pin@32||3.5|-0.75|pin@15||3.5|4.5
Awire|net@51|||1800|pin@32||3.5|-0.75|NAND@0|A|5.5|-0.75
Awire|net@52|||0|pin@24||16.5|-8.75|pin@22||3.75|-8.75
Awire|net@53|||1800|pin@39||-42.75|-30.75|M6|g|-40.25|-30.75
Awire|net@54|||2700|M5|d|-37.25|-21|pwr@4||-37.25|-18.25
Awire|net@55|||2700|gnd@2||-37.25|-34.5|M6|s|-37.25|-32.75
Awire|net@56|||0|M5|g|-40.25|-23|pin@38||-42.75|-23
Awire|net@57|||900|pin@37||-42.75|-26.5|pin@39||-42.75|-30.75
Awire|net@58|||900|pin@38||-42.75|-23|pin@37||-42.75|-26.5
Awire|net@61|||2700|pin@41||-47|-26.5|pwr@5||-47|-18.5
Awire|net@62|||0|pin@37||-42.75|-26.5|pin@41||-47|-26.5
Awire|net@63|||2700|pin@47||-37.25|-27|M5|s|-37.25|-25
Awire|net@64|||1800|M8|g|7.25|-30.75|pin@42||8|-30.75
Awire|net@65|||0|pin@43||8|-23.75|M7|g|7.25|-23.75
Awire|net@66|||2700|gnd@3||4.25|-34.75|M8|s|4.25|-32.75
Awire|net@67|||2700|pin@42||8|-30.75|pin@44||8|-27
Awire|net@68|||2700|pin@44||8|-27|pin@43||8|-23.75
Awire|net@71|||2700|gnd@4||12|-29.5|pin@46||12|-27
Awire|net@72|||2700|M7|d|4.25|-21.75|pwr@6||4.25|-18.5
Awire|net@73|||1800|pin@44||8|-27|pin@46||12|-27
Awire|net@74|||2700|pin@48||4.25|-27.25|M7|s|4.25|-25.75
Awire|net@75|||2700|M6|d|-37.25|-28.75|pin@47||-37.25|-27
Awire|net@77|||2700|M8|d|4.25|-28.75|pin@48||4.25|-27.25
X

# Cell fig16.38;1{sch}
Cfig16.38;1{sch}||schematic|1181688858343|1183056597015|
NTransistor|M1|D5G1;X1;Y-3;|-21.75|-9|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M2|D5G1;X1;Y-3;|-11|-9|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|M3|D5G1;X1.75;Y-2.75;|-21.75|11.25|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|M4|D5G1;X2;Y-2.75;|-11|11.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MB1|D5G1;X1;Y-3;|-25.75|-14.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MB2|D5G1;X1;Y-3;|-7|-14.25|||YRRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS1|D5G1;X1;Y-3;|-25.75|2.25|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS2|D5G1;X1;Y-3;|-11|2.25|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G0.5;X-1;Y-3.25;)SN_50n
NTransistor|MS3|D5G1;X1.75;Y-2.75;|-32.75|11.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
NTransistor|MS4|D5G1;X1.75;Y-3;|-0.5|12|||YRRR|2|ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D40.0|SIM_spice_model(D5G0.5;X-1;Y-2.25;)SP_50n
INAND;1{ic}|NAND@0||8.25|0.25|||D5G4;
INAND;1{ic}|NAND@1||8.25|-11.75|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-23.75|-20||||
NGround|gnd@1||-9|-19.75||||
NWire_Pin|pin@0||-15.5|-9||||
NWire_Pin|pin@1||-17.5|-9||||
NWire_Pin|pin@2||-9|8||||
NWire_Pin|pin@3||-15.25|11.5||||
NWire_Pin|pin@4||-15.25|7.75||||
NWire_Pin|pin@5||-23.75|7.75||||
NWire_Pin|pin@6||-17.5|5.75||||
NWire_Pin|pin@7||-14.5|8||||
NWire_Pin|pin@8||-34.25|-14.5||||
NWire_Pin|pin@9||1.75|-14.25||||
NWire_Pin|pin@10||-35.25|11.5||||
NWire_Pin|pin@11||-35.25|2.25||||
NWire_Pin|pin@12||-30.75|7.75||||
NWire_Pin|pin@13||-33.5|7.75||||
NWire_Pin|pin@14||-14.5|11.25||||
NWire_Pin|pin@15||3|8||||
NWire_Pin|pin@16||-2.5|8||||
NWire_Pin|pin@17||1|2.25||||
NWire_Pin|pin@18||1|12||||
NWire_Pin|pin@19||-38.5|2.25||||
NWire_Pin|pin@20||3|0.5||||
NWire_Pin|pin@21||3.25|-9.25||||
NWire_Pin|pin@22||3.25|-5.25||||
NWire_Pin|pin@23||16|1.5||||
NWire_Pin|pin@24||16|-5.25||||
NWire_Pin|pin@25||-33.5|-11.5||||
NWire_Pin|pin@26||3|-3.25||||
NWire_Pin|pin@27||18.5|1.5||||
NWire_Pin|pin@28||18.75|-10.5||||
NWire_Pin|pin@29||-9|5.75||||
NWire_Pin|pin@30||16.5|-3.25||||
NWire_Pin|pin@31||16.5|-10.5||||
NWire_Pin|pin@32||3|2.75||||
Ngeneric:Invisible-Pin|pin@33||17|14.5|||||SIM_spice_card(D5G1;)S[VVDD VDD 0 DC 1,VGND GND 0 DC 0,VCLK CLK 0 DC 0 PULSE 0  1 0 10p 10p 5n 10n,VInP InP 0 DC 0 PULSE .4 .6 5n 0 0 4n 12n,VInN InN 0 DC 500m,.include cmosedu_models.txt,.tran 10p  50n 0 uic,.options post]
Ngeneric:Invisible-Pin|pin@34||-14.5|21.75|||||ART_message(D5G2;)SPlot CLK InP+1.25 InN+1.25 Q+2.5
NWire_Pin|pin@35||-15.5|5.25||||
NWire_Pin|pin@36||-23.75|5.25||||
NPower|pwr@0||-23.75|17.25||||
NPower|pwr@1||-9|17.5||||
NPower|pwr@2||-30.75|17.25||||
NPower|pwr@3||-2.5|17.25||||
Awire|CLK|D5G1.5;X-2.75;Y0.75;||1800|pin@19||-38.5|2.25|pin@11||-35.25|2.25
Awire|InN|D5G1.5;Y0.75;||1800|MB2|g|-6|-14.25|pin@9||1.75|-14.25
Awire|InP|D5G1.5;X-3.5;Y1;||0|MB1|g|-26.75|-14.5|pin@8||-34.25|-14.5
Awire|OutN|D5G1.5;X35.75;Y-18.75;||0|pin@12||-30.75|7.75|pin@13||-33.5|7.75
Awire|OutP|D5G1.5;X5;Y-4.25;||0|pin@15||3|8|pin@16||-2.5|8
Awire|Q|D5G1.5;X1.5;Y0.25;||1800|pin@31||16.5|-10.5|pin@28||18.75|-10.5
Awire|Qbar|D5G1.5;X1.75;Y0.25;||1800|pin@23||16|1.5|pin@27||18.5|1.5
Awire|net@0|||0|M2|g|-12|-9|pin@0||-15.5|-9
Awire|net@1|||0|NAND@1|B|5|-11.5|pin@25||-33.5|-11.5
Awire|net@2|||2700|MB1|d|-23.75|-12.5|M1|s|-23.75|-11
Awire|net@3|||2700|MS4|d|-2.5|14|pwr@3||-2.5|17.25
Awire|net@4|||1800|M1|g|-20.75|-9|pin@1||-17.5|-9
Awire|net@5|||2700|M3|d|-23.75|13.25|pwr@0||-23.75|17.25
Awire|net@6|||900|pwr@1||-9|17.5|M4|d|-9|13.5
Awire|net@7|||2700|pin@1||-17.5|-9|pin@6||-17.5|5.75
Awire|net@8|||2700|pin@0||-15.5|-9|pin@35||-15.5|5.25
Awire|net@9|||0|pin@35||-15.5|5.25|pin@36||-23.75|5.25
Awire|net@10|||1800|pin@6||-17.5|5.75|pin@29||-9|5.75
Awire|net@11|||900|M4|s|-9|9.5|pin@2||-9|8
Awire|net@12|||0|M4|g|-12|11.5|pin@3||-15.25|11.5
Awire|net@13|||900|pin@3||-15.25|11.5|pin@4||-15.25|7.75
Awire|net@14|||0|pin@4||-15.25|7.75|pin@5||-23.75|7.75
Awire|net@15|||2700|pin@5||-23.75|7.75|M3|s|-23.75|9.25
Awire|net@16|||2700|pin@36||-23.75|5.25|pin@5||-23.75|7.75
Awire|net@17|||900|pin@2||-9|8|pin@29||-9|5.75
Awire|net@18|||1800|M3|g|-20.75|11.25|pin@14||-14.5|11.25
Awire|net@19|||2700|gnd@0||-23.75|-18|MB1|s|-23.75|-16.5
Awire|net@20|||2700|gnd@1||-9|-17.75|MB2|s|-9|-16.25
Awire|net@21|||2700|MB2|d|-9|-12.25|M2|s|-9|-11
Awire|net@22|||2700|MS2|d|-9|4.25|pin@29||-9|5.75
Awire|net@23|||0|MS2|g|-12|2.25|MS1|g|-26.75|2.25
Awire|net@24|||900|MS2|s|-9|0.25|M2|d|-9|-7
Awire|net@25|||900|pin@14||-14.5|11.25|pin@7||-14.5|8
Awire|net@26|||2700|M1|d|-23.75|-7|MS1|s|-23.75|0.25
Awire|net@27|||2700|MS1|d|-23.75|4.25|pin@36||-23.75|5.25
Awire|net@28|||0|MS1|g|-26.75|2.25|pin@11||-35.25|2.25
Awire|net@29|||0|MS3|g|-33.75|11.5|pin@10||-35.25|11.5
Awire|net@30|||900|pin@10||-35.25|11.5|pin@11||-35.25|2.25
Awire|net@31|||0|pin@5||-23.75|7.75|pin@12||-30.75|7.75
Awire|net@32|||2700|pin@12||-30.75|7.75|MS3|s|-30.75|9.5
Awire|net@33|||0|pin@2||-9|8|pin@7||-14.5|8
Awire|net@34|||2700|MS3|d|-30.75|13.5|pwr@2||-30.75|17.25
Awire|net@35|||0|pin@16||-2.5|8|pin@2||-9|8
Awire|net@36|||900|MS4|s|-2.5|10|pin@16||-2.5|8
Awire|net@37|||1800|MS2|g|-12|2.25|pin@17||1|2.25
Awire|net@38|||2700|pin@17||1|2.25|pin@18||1|12
Awire|net@39|||1800|MS4|g|0.5|12|pin@18||1|12
Awire|net@40|||0|NAND@0|B|5|0.5|pin@20||3|0.5
Awire|net@41|||0|NAND@1|A|5|-9.25|pin@21||3.25|-9.25
Awire|net@42|||2700|pin@21||3.25|-9.25|pin@22||3.25|-5.25
Awire|net@43|||1800|NAND@0|Out|13.25|1.5|pin@23||16|1.5
Awire|net@44|||900|pin@23||16|1.5|pin@24||16|-5.25
Awire|net@45|||900|pin@13||-33.5|7.75|pin@25||-33.5|-11.5
Awire|net@46|||1800|NAND@1|Out|13.25|-10.5|pin@31||16.5|-10.5
Awire|net@47|||900|pin@30||16.5|-3.25|pin@31||16.5|-10.5
Awire|net@48|||900|pin@20||3|0.5|pin@26||3|-3.25
Awire|net@49|||1800|pin@26||3|-3.25|pin@30||16.5|-3.25
Awire|net@50|||2700|pin@32||3|2.75|pin@15||3|8
Awire|net@51|||1800|pin@32||3|2.75|NAND@0|A|5|2.75
Awire|net@52|||0|pin@24||16|-5.25|pin@22||3.25|-5.25
X

# Cell fig16.65;1{sch}
Cfig16.65;1{sch}||schematic|1181689359703|1182809485250|
N4-Port-Transistor|M1|D5G1;X1.5;Y-3.25;|-20|-1.25|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X-1.75;Y-3;)SN_50n
NResistor|R1|D5G1;Y-2;|-18|-7|||R||SCHEM_resistance(D5G1;)S1G
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-18|-12.5||||
NGround|gnd@1||-9|-2.25||||
NGround|gnd@2||-12.5|-5.75||||
NWire_Pin|pin@0||-25|-1.25||||
NWire_Pin|pin@3||-18|1.25||||
NWire_Pin|pin@4||-9|1.25||||
Ngeneric:Invisible-Pin|pin@5||-19.25|4|||||ART_message(D5G1;)SPlot -I(VGS)
Ngeneric:Invisible-Pin|pin@6||-28.5|-5.5|||||SIM_spice_card(D5G1;)S[VGS VGS 0 DC 1,VGND GND 0 DC 0,.dc  VGS 0 2 1m,.options post,.include cmosedu_models.txt]
NWire_Pin|pin@7||-12.5|-2.25||||
Awire|VGS|D5G1;X-2;Y0.5;||0|M1|g|-21|-1.25|pin@0||-25|-1.25
Awire|net@1|||2700|R1|b|-18|-5|M1|s|-18|-3.25
Awire|net@5|||2700|M1|d|-18|0.75|pin@3||-18|1.25
Awire|net@6|||1800|pin@3||-18|1.25|pin@4||-9|1.25
Awire|net@7|||900|pin@4||-9|1.25|gnd@1||-9|-0.25
Awire|net@8|||2700|gnd@0||-18|-10.5|R1|a|-18|-9
Awire|net@12|||1800|M1|b|-18|-2.25|pin@7||-12.5|-2.25
Awire|net@15|||2700|gnd@2||-12.5|-3.75|pin@7||-12.5|-2.25
X

# Cell fig16.66;1{sch}
Cfig16.66;1{sch}||schematic|1181689384062|1208961115515|
N4-Port-Transistor|M1|D5G1;X1.5;Y-3.25;|-14.25|6.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X-1.75;Y-3;)SN_50n
NResistor|R1|D5G1;Y-2;|-12.25|0.75|||R||SCHEM_resistance(D5G1;)S1G
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||-12.25|-4.75||||
NGround|gnd@2||-6.75|2||||
NWire_Pin|pin@0||-19.25|6.5||||
Ngeneric:Invisible-Pin|pin@3||-12|14.5|||||ART_message(D5G1;)SPlot -I(VGS)
Ngeneric:Invisible-Pin|pin@4||-24.25|2.5|||||SIM_spice_card(D5G1;)S[VDD VDD 0 DC 1,VGS VGS 0 DC 1,VGND GND 0 DC 0,.dc  VGS 0 2 1m,.options post,.include cmosedu_models.txt]
NWire_Pin|pin@5||-6.75|5.5||||
NPower|pwr@0||-12.25|12.25||||
Awire|VGS|D5G1;X-2;Y0.5;||0|M1|g|-15.25|6.5|pin@0||-19.25|6.5
Awire|net@0|||2700|R1|b|-12.25|2.75|M1|s|-12.25|4.5
Awire|net@1|||1800|M1|b|-12.25|5.5|pin@5||-6.75|5.5
Awire|net@2|||2700|gnd@2||-6.75|4|pin@5||-6.75|5.5
Awire|net@6|||2700|gnd@0||-12.25|-2.75|R1|a|-12.25|-1.25
Awire|net@15|||2700|M1|d|-12.25|8.5|pwr@0||-12.25|12.25
X

# Cell fig16.67;1{sch}
Cfig16.67;1{sch}||schematic|1181689390890|1208961276125|
N4-Port-Transistor|M1|D5G1;X1.5;Y-3.25;|-12.25|-1.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D20.0|SIM_spice_model(D5G1;X0.5;Y-2.25;)SN_50n
NResistor|R1|D5G1;Y-2;|-10.25|-7.25|||R||SCHEM_resistance(D5G1;)S1G
NResistor|R2|D5G1;Y2.25;|-10.25|4|||RRR||SCHEM_resistance(D5G1;)S1G
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@5||-10.25|-12.75||||
NGround|gnd@6||-10.25|9.5|||RR|
Ngeneric:Invisible-Pin|pin@3||-3.5|6.25|||||ART_message(D5G1;)SPlot -I(VGS)
Ngeneric:Invisible-Pin|pin@4||-20.75|5|||||SIM_spice_card(D5G1;)S[VB VB  0 DC 1,VGS VGS 0 DC 0,VGND GND 0 DC 0,.dc  Vb 0 2 1m,.options post,.include cmosedu_models.txt]
NWire_Pin|pin@5||-2.25|-2.5||||
NWire_Pin|pin@8||-17.75|-1.5||||
Awire|VB|D5G1;X3.5;Y0.5;||1800|M1|b|-10.25|-2.5|pin@5||-2.25|-2.5
Awire|VGS|D5G1;X-2;Y1;||0|M1|g|-13.25|-1.5|pin@8||-17.75|-1.5
Awire|net@18|||2700|gnd@5||-10.25|-10.75|R1|a|-10.25|-9.25
Awire|net@19|||2700|R1|b|-10.25|-5.25|M1|s|-10.25|-3.5
Awire|net@20|||900|gnd@6||-10.25|7.5|R2|a|-10.25|6
Awire|net@21|||2700|M1|d|-10.25|0.5|R2|b|-10.25|2
X

# Cell mbit;1{lay}
Cmbit;1{lay}||mocmos|1220033936933|1220034413398||DRC_last_good_drc_area_date()G1220034422065|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1220034422065
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-N-Active-Con|contact@0||5.25|-2.75|5|||
NN-Transistor|nmos@0||5.25|1.25|7||||SIM_spice_model(D5G1;)SN_50n
NN-Transistor|nmos@1||5.25|10.25|7|8|||SIM_spice_model(D5G1;)SN_50n
NPolysilicon-1-Pin|pin@0||-0.75|1.25||||
NPolysilicon-1-Pin|pin@1||-0.75|10.25||||
APolysilicon-1|net@0|||IJS1800|nmos@0|poly-left|-1.75|1.25|pin@0||-0.75|1.25
APolysilicon-1|net@2||8|IJS1800|nmos@1|poly-left|-1.75|10.25|pin@1||-0.75|10.25
AN-Active|net@3|||S2700|nmos@1|diff-bottom|4.75|2.25|nmos@0|diff-top|4.75|5
AN-Active|net@4|||S2700|contact@0||5|-3|nmos@0|diff-bottom|5|-2.5
Ebl||D5G2;|contact@0||B
Evdd||D5G2;|pin@1||B
Ewl||D5G2;|pin@0||B
X

# Cell mbit;1{sch}
Cmbit;1{sch}||schematic|1220033422744|1220921791192|
Ngeneric:Facet-Center|art@0||0|0||||AV
NGround|gnd@0||1.5|5||||
NTransistor|nmos@0||3.5|3.5|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;X-1;Y-1.75;)SN_50n
NTransistor|nmos@2||7.5|5.25|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D10.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;X-1;Y-1.75;)SN_50n
NWire_Pin|pin@0||1|1.5||||
NWire_Pin|pin@1||3.5|4.75||||
NWire_Pin|pin@4||7.5|6.75||||
Awire|net@0|||0|nmos@0|s|1.5|1.5|pin@0||1|1.5
Awire|net@1|||2700|nmos@0|g|3.5|4.5|pin@1||3.5|4.75
Awire|net@6|||2700|nmos@2|g|7.5|6.25|pin@4||7.5|6.75
Awire|net@7|||900|nmos@2|s|5.5|3.25|nmos@0|d|5.5|1.5
Ebit|bl|D5G0.5;|pin@0||B
Evdd||D5G0.5;|pin@4||B
Ewl||D5G0.5;|pin@1||B
X

# Cell mbit_jake;1{ic}
Cmbit_jake;1{ic}||artwork|1220922175019|1220922405131|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Polygon|art@2||-0.25|-1.25|6.5|1.5|||trace()V[-3.25/-0.25,-1.25/-0.25,-1.25/0.75,1.75/0.75,1.75/-0.25,3.25/-0.25,3.25/-0.75,3.25/0.25]
NOpened-Polygon|art@3||4|-1.5|1|1|||trace()V[-0.5/-0.5,-0.5/0.5,-0.5/0,0.5/0]
NOpened-Polygon|art@4||0|0.75|3|1.5|||trace()V[-1.5/-0.75,1.5/-0.75,0/-0.75,0/0.75]
Nschematic:Bus_Pin|pin@0||-3.5|-1.5||||
Nschematic:Wire_Pin|pin@1||-3.5|-1.5||||
Nschematic:Bus_Pin|pin@2||4.5|-1.5||||
Nschematic:Wire_Pin|pin@3||4.5|-1.5||||
Nschematic:Bus_Pin|pin@4||0|1.5|||R|
Nschematic:Wire_Pin|pin@5||0|1.5|||R|
Aschematic:wire|net@0|||2700|pin@1||-3.5|-1.5|pin@0||-3.5|-1.5
Aschematic:wire|net@1|||2700|pin@3||4.5|-1.5|pin@2||4.5|-1.5
Aschematic:wire|net@2|||0|pin@5||0|1.5|pin@4||0|1.5
Ebit||D5G2;|pin@0||B
Evdd||D5G2;|pin@2||B
Ewl||D5G2;|pin@4||B
X

# Cell mbit_jake;1{lay}
Cmbit_jake;1{lay}||mocmos|1220922442658|1220923850554||DRC_last_good_drc_area_date()G1220923012413|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1220923888014
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-N-Active-Con|contact@0||1.5|-3.75|5|||
NN-Transistor|nmos@0||1.5|1|7||||SIM_spice_model(D5G1;)SN_50n
NN-Transistor|nmos@2||1.5|11|7|8|||SIM_spice_model(D5G1;)SN_50n
NP-Well-Node|plnode@0||14.75|7|12|36||A
NMetal-1-P-Well-Con|well@0||15.5|-6.75||||
AN-Active|net@0|||S2700|nmos@2|diff-bottom|1.5|3.25|nmos@0|diff-top|1.5|4.75
AN-Active|net@2|||S900|nmos@0|diff-bottom|1.5|-2.75|contact@0||1.5|-3.25
Ebit||D5G2;|contact@0||B
Egnd||D5G2;|well@0||G
Evdd||D5G2;|nmos@2|poly-left|P
Evdd_1||D5G2;|nmos@2|poly-right|B
Ewl||D5G2;|nmos@0|poly-left|B
Ewl_1||D5G2;|nmos@0|poly-right|B
X

# Cell mbit_jake;1{sch}
Cmbit_jake;1{sch}||schematic|1220921971241|1220922789003|
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||-4|0||||
NOff-Page|conn@1||-4|4||||
NOff-Page|conn@2||-4|7.5||||
NGround|gnd@1||0.25|-2.25|-1.5|-1.5||
NGround|gnd@2||5.25|-2.25|-1.5|-1.5||
Imbit_jake;1{ic}|mbit_jak@0||4.5|12.5|||D5G4;
N4-Port-Transistor|nmos-4@0||1.25|2|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;X-1;Y-1.75;)SN_50n
N4-Port-Transistor|nmos-4@1||6.25|2|||||ATTR_length(D5G0.5;X-0.5;Y-1;)D10.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;X-1;Y-1.75;)SN_50n
NWire_Pin|pin@0||1.25|4||||
NWire_Pin|pin@1||6.25|7.5||||
Awire|net@1|||0|nmos-4@1|s|4.25|0|nmos-4@0|d|3.25|0
Awire|net@3|||1800|conn@0|y|-2|0|nmos-4@0|s|-0.75|0
Awire|net@4|||1800|conn@1|y|-2|4|pin@0||1.25|4
Awire|net@5|||900|pin@0||1.25|4|nmos-4@0|g|1.25|3
Awire|net@6|||1800|conn@2|y|-2|7.5|pin@1||6.25|7.5
Awire|net@7|||900|pin@1||6.25|7.5|nmos-4@1|g|6.25|3
Awire|net@11|||2700|gnd@1||0.25|-1|nmos-4@0|b|0.25|0
Awire|net@14|||2700|gnd@2||5.25|-1|nmos-4@1|b|5.25|0
Ebit||D5G2;X1.5;|conn@0|a|B
Evdd||D5G2;X1.5;|conn@2|a|B
Ewl||D5G2;X1.5;|conn@1|a|B
X

# Cell nSA;1{sch}
CnSA;1{sch}||schematic|1219711616188|1219714943002|
Ngeneric:Facet-Center|art@0||0|0||||AV
NCapacitor|cap@0||9.75|3.25|||||SCHEM_capacitance(D5G1;)S0.2p
NCapacitor|cap@1||27|3.5|||||SCHEM_capacitance(D5G1;)S0.2p
NGround|gnd@1||9.75|-2||||
NGround|gnd@3||27|-1.75||||
NGround|gnd@4||-0.5|-19.75||||
NTransistor|nmos@0||21.75|-6.25|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.75;)SN_50n
NTransistor|nmos@1||14.5|-6.25|||RRR||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.75;)SN_50n
NTransistor|nmos@2||-2.5|-14.75|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)D2.0|ATTR_width(D5G1;X0.5;Y-1;)D10.0|SIM_spice_model(D5G0.5;RRRX-1;Y-1.75;)SN_50n
NWire_Pin|pin@1||9.75|6.75||||
NWire_Pin|pin@4||27|7||||
NWire_Pin|pin@5||23.75|7||||
NWire_Pin|pin@6||12.5|6.75||||
NWire_Pin|pin@7||16.75|-6.25||||
NWire_Pin|pin@8||16.75|-0.5||||
NWire_Pin|pin@9||23.75|-0.5||||
NWire_Pin|pin@10||19.25|-6.25||||
NWire_Pin|pin@11||19.25|-2||||
NWire_Pin|pin@12||12.5|-2||||
NWire_Pin|pin@13||12.5|-10.5||||
NWire_Pin|pin@14||23.75|-10.5||||
NWire_Pin|pin@15||-0.5|-10.5||||
NWire_Pin|pin@16||-6.5|-14.75||||
Ngeneric:Invisible-Pin|pin@17||7.5|-14|||||SIM_spice_card(D5G1;)S[.ic v(bit0)=400m v(bit1)=500m,vin NSA 0 pulse 0 1 5n 100p,.include cmosedu_models.txt,.tran 100p 20n UIC]
Awire|NLAT|D5G1;||1800|pin@15||-0.5|-10.5|pin@13||12.5|-10.5
Awire|NSA|D5G1;||0|nmos@2|g|-3.5|-14.75|pin@16||-6.5|-14.75
Awire|bit0|D5G1;||0|pin@6||12.5|6.75|pin@1||9.75|6.75
Awire|bit1|D5G1;||1800|pin@5||23.75|7|pin@4||27|7
Awire|net@3|||900|pin@1||9.75|6.75|cap@0|a|9.75|5.25
Awire|net@4|||900|cap@0|b|9.75|1.25|gnd@1||9.75|0
Awire|net@9|||900|pin@4||27|7|cap@1|a|27|5.5
Awire|net@10|||900|cap@1|b|27|1.5|gnd@3||27|0.25
Awire|net@11|||2700|pin@9||23.75|-0.5|pin@5||23.75|7
Awire|net@13|||2700|pin@12||12.5|-2|pin@6||12.5|6.75
Awire|net@15|||1800|nmos@1|g|15.5|-6.25|pin@7||16.75|-6.25
Awire|net@16|||2700|pin@7||16.75|-6.25|pin@8||16.75|-0.5
Awire|net@17|||2700|nmos@0|d|23.75|-4.25|pin@9||23.75|-0.5
Awire|net@18|||1800|pin@8||16.75|-0.5|pin@9||23.75|-0.5
Awire|net@19|||0|nmos@0|g|20.75|-6.25|pin@10||19.25|-6.25
Awire|net@20|||2700|pin@10||19.25|-6.25|pin@11||19.25|-2
Awire|net@21|||2700|nmos@1|s|12.5|-4.25|pin@12||12.5|-2
Awire|net@22|||0|pin@11||19.25|-2|pin@12||12.5|-2
Awire|net@23|||900|nmos@1|d|12.5|-8.25|pin@13||12.5|-10.5
Awire|net@24|||1800|pin@13||12.5|-10.5|pin@14||23.75|-10.5
Awire|net@25|||2700|pin@14||23.75|-10.5|nmos@0|s|23.75|-8.25
Awire|net@26|||2700|gnd@4||-0.5|-17.75|nmos@2|s|-0.5|-16.75
Awire|net@28|||2700|nmos@2|d|-0.5|-12.75|pin@15||-0.5|-10.5
X

# Cell sim1;1{lay}
Csim1;1{lay}||mocmos|1220924258735|1220924806200||DRC_last_good_drc_area_date()G1220924795580
Iarray_jake;1{lay}|array_ja@0||11.5|5.5|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-N-Active-Con|contact@3||36.75|-21.75||||
NMetal-1-N-Active-Con|contact@4||20|-22.75||||
NMetal-1-N-Active-Con|contact@5||28.25|-24||5||
NN-Transistor|nmos@0||23.75|-24|7||R||SIM_spice_model(D5G1;)SN_50n
NN-Transistor|nmos@1||33|-24|7||R||SIM_spice_model(D5G1;)SN_50n
NMetal-2-Pin|pin@0||-2|-22.25||||
NMetal-1-Pin|pin@1||13.5|-22.75||||
NMetal-1-Pin|pin@2||43|-21.75||||
NPolysilicon-1-Pin|pin@3||-25.25|7||||
NMetal-1-Pin|pin@4||-25.25|17.25||||
NPolysilicon-1-Pin|pin@5||-26|44.25||||
NPolysilicon-1-Pin|pin@6||-24.25|81.5||||
NPolysilicon-1-Pin|pin@7||-25.5|118.75||||
Ngeneric:Invisible-Pin|pin@8||-79|89.25|||||SIM_spice_card(D5G4;)S[VDD VDD 0 DC 1,VDDby2 vddby2 0 DC 0.5,Vw0 w0 0 DC 0,Vw1 w1 0 DC 0,Vw2 w2 0 DC 0,Vw3 w3 0 DC 0,Veq eq 0 DC 0 pulse 0 1 5n 100p 100p 5n,.include cmosedu_models.txt]
NPolysilicon-1-Pin|pin@11||5.25|-31||||
NMetal-1-Pin|pin@12||28.25|-37.75||||
AMetal-1|b0|D5G4;||S900|array_ja@0|b0|13.5|-12.25|pin@1||13.5|-22.75
AMetal-1|b1|D5G4;||S900|array_ja@0|b1|43|-12.5|pin@2||43|-21.75
AMetal-2|gnd|D5G4;||S900|array_ja@0|gnd|-2|-12.5|pin@0||-2|-22.25
AN-Active|net@13||7|IJS0|nmos@1|diff-top|29|-24|nmos@0|diff-bottom|27.5|-24
AMetal-1|net@16|||S0|pin@2||43|-21.75|contact@3||36.75|-21.75
AN-Active|net@17|||S0|nmos@1|diff-bottom|36.75|-21.75|contact@3||36.75|-21.75
AMetal-1|net@18|||S1800|pin@1||13.5|-22.75|contact@4||20|-22.75
AN-Active|net@19|||S0|nmos@0|diff-top|20|-22.75|contact@4||20|-22.75
APolysilicon-1|net@20|||S0|nmos@1|poly-left|33|-31|nmos@0|poly-left|23.75|-31
APolysilicon-1|net@21|||S0|nmos@0|poly-left|23.75|-31|pin@11||5.25|-31
AMetal-1|net@22|||S2700|pin@12||28.25|-37.75|contact@5||28.25|-27
AN-Active|net@23||7|S1800|nmos@0|diff-bottom|27.5|-27|contact@5||28.25|-27
AMetal-1|vdd|D5G1;||S0|array_ja@0|vdd|-14.75|17.25|pin@4||-25.25|17.25
APolysilicon-1|w0|D5G1;||S0|array_ja@0|wl0|-2.75|7|pin@3||-25.25|7
APolysilicon-1|w1|D5G1;||S0|array_ja@0|wl1|-3.75|44.25|pin@5||-26|44.25
APolysilicon-1|w2|D5G1;||S0|array_ja@0|wl2|-4.25|81.5|pin@6||-24.25|81.5
APolysilicon-1|w3|D5G1;||S0|array_ja@0|wl3|-3.5|118.75|pin@7||-25.5|118.75
EEq||D5G2;|pin@11||P
Evddby2||D5G2;|pin@12||P
X