Homework assignments and Project Information for ECE 5/418 Memory Circuit Design, Fall 2008

Homework guidelines are found here.

Project – Report, in PDF, and zipped file containing: *.jelib, *.plt files, and simulation netlists emailed to me before the start of class on Wednesday, Dec. 3.

Using the process used in HW#8 design, layout, and simulate a DS sensing circuit that can be used to determine the threshold voltage of a FG device made using the same process (poly2 is the WL and poly1 is the floating gate). Do not design or use a counter to determine the sense’s output. Rather use an RC circuit to take the average of the sense-amp’s output in the simulations (use SPICE code in Electric so your cells LVS). The size of the memory device is 6/2 lambdas to pass DRCs. Assume your memory cell is programmed with positive threshold voltages so that leaving a WL at ground keeps the unselected devices off. To keep things simple use a normal NMOS device for the FG memory cell (so the models below can be used). Layout an array that has 8 WLs and 8 BLs. Memory cell ground connection can use n+. Layout the sense amps on pitch with the BLs. To simulate the sense-amp’s operation use SPICE code to add a current sink to the bit lines. It’s also ok to use SPICE code to add 1 pF of capacitance to the BLs. If you use a reference make sure it’s in your schematic and layout not in SPICE code.

How does your design perform with different VDDs? Note that for this design you can change the BL current to simulate various WL voltages used to vary the memory cell’s current. Your report, 10 pages or less, should detail your design considerations (why you selected what you did and the trade-offs), simulation schematics with results, and provide a table summarizing the results (sensitivity to VDD, resolution vs. sense time, bitline variation vs bitline capacitance, power, size, etc.) Plots showing how one parameter is a function of some other parameter are a good idea (sense time vs operating frequency, or BL variation vs operating frequency for varying bitline capacitance). This is not a team effort. A significant portion of your grade will be based on the quality of your report.

HW#8 – due Wednesday, October 29, Design and simulate a Flash DS sensing circuit that holds the bitline at 2.5V. Assume the maximum current the memory cell will pull is 5 uA. Use ON’s 500 nm (C5 with two polysilicon layers, 3 levels of metal, and VDD = 5 V) with a lambda, using the MOSIS design rules, of 300 nm (minimum L is 600 nm). MOSIS information for this process is located here and the SPICE models are in C5_models.txt. No jelib or SPICE netlists need to be emailed; however, you do need to turn in schematics, design considerations, and simulation results. Make sure you state all of your assumptions and why you made them. In anticipation of the projects use Electric for schematic capture and to generate netlists. Note that both the schematic and technology should be set to “mocmos”. The scale should be 300 nm (if this doesn’t make sense ask in class).

HW#7 – due Wednesday, October 15, design a DLL for a DRAM with a tCK of 1.5 ns using the 50 nm process. State your assumptions (e.g., input and output buffer delays, how these delays are modeled in the feedback path of the DLL, etc.). Email me the jelib and the *.plt (for plotting in LTspice) so plotting and simulating are easy (zip up the folder holding everything and email it to me). The report (a PDF you email along with the zip) you turn in should provide your design considerations and simulation results (this HW will count for considerably more than the other homework assignments). Note that this one time only you are being asked to turn in a PDF file instead of paper.

HW#6 – due Monday, October 6, use Electric and LTspice to design and simulate a shift register (shift-right and shift-left) and a delay element (delay line) for use in a registered-controlled DLL. The shift-register bit, delay stage, and total design should all have icon views. Use 16 stages to simulate the operation of your design (schematics only, no layout, and only using LTspice, not IRSIM). The top level simulation schematic should hold one icon that contains the shift-register icon and delay line icon. The inputs to this top-level icon are CLKin, SR, SL, and clock (for shifting). The output of the icon is CLKout. Email me the jelib and the *.plt (for plotting in LTspice) so plotting and simulating are easy (zip up the folder holding everything and email it to me).

HW#5 – due Wednesday, October 1, use Electric to capture the schematic of a phase detector, PD, for use in a registered controlled DLL (outputs of the PD are shift-right, shift-left, or don’t shift). The PD you design should have an icon view that can be used in simulations. Further, the gates and flip-flops used in the PD should also have icon views that can be used in the schematic of the PD. Simulate the operation of PD using both LTspice and IRSIM ensuring your understanding is clear in what you turn in on paper and your simulation cells in the library. Email me the jelib and the *.plt (for plotting in LTspice) and control files for IRSIM so plotting and simulating are easy (zip up everything and email it to me…should be under 500k in size).

HW#4 - due Wednesday, September 24, A16.3 and explain, in your own word, which circuits in a DRAM influence (and how they influence): t_RC, t_RAS, t_CAS, t_ASR, t_RAH, t_ASC, and t_CAH. Assume the DRAM is second generation (not a synchronous part).

HW#3 – due Wednesday, Septemeber 17, design, layout, and simulate a 128-bit DRAM memory made using two 8 by 8 DRAM arrays (assume an 8 by 1 page size). Assume an Open Array architecture is used. Show how your design operates by simulating the schematic and layout. Show both writing and reading. Send me your jelib making sure that the cells used for simulations are easy to identify. Also, make sure that it’s clear you understand the sequence of events (EQ, Wordline, NSA, etc.) Feel free to send the jelib in a zipped folder so you can include the LTspice *.plt files.

HW#2 – due Wednesday, September 10, problem A16.12 and layout of the circuit seen in Fig. A16.12 making sure to state all of your assumptions (e.g. how you are implementing the capacitors). DRC and LVS your design. Email me your jelib, with the name of the cell (layout and schematic) we should simulate, LVS, and DRC, so I can forward to the grader. Note that both the layout and schematic should simulate. Use SPICE code to add the loading from the bitline capacitors (don’t layout the bitline capacitors or include them in your schematic).

HW#1 – due Friday, September 5, (or Wednesday, September 3, if you won’t be in class on Friday) Estimate, using hand calculations, Electric, and LTspice, how to determine the effective switching resistances of the 50 nm NMOS and PMOS used in this class. Verify your estimates with MOSFETs driving 100 fF load capacitances. A16.8, A16.9, A16.10, A16.11.

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