Homework assignments for ECE 614 Advanced Analog IC Design, Fall 2009
Homework guidelines are found here.
HW#8 Monday, Nov. 30, repeat HW#6 for the
following Ch. 29 problems
LB 24, 30 (Check 29, 35, 36)
SB 25, 31 (Check 28, 34, 37)
CG 26, 32, 39 (Check 27, 33, 38)
QH 27, 33, 38 (Check 26, 32, 39)
AJ 28, 34, 37 (Check 24, 30)
JW 29, 35, 36 (Check 25, 31)
HW#7 Monday, Nov. 16, repeat HW#6 for the
following Ch. 29 problems
LB 6, 12, 18 (Check 5, 11, 17, 23)
SB 1, 7, 13, 19 (Check 4, 10, 16, 22)
CG 2, 8, 14, 20 (Check 3, 9, 15, 21)
QH 3, 9, 15, 21 (Check 2, 8, 14, 20)
AJ 4, 10, 16, 22 (Check 1, 7, 13, 19)
JW 5, 11, 17, 23 (Check 6, 12, 18)
HW#6 Monday, Nov. 9, redo problems from book Ch. 28 to replace online
solutions (email me a separate PDF for each solution with a name like
P28.1, P28.2, etc.)
Please put your name on your solution but do not put the class number,
date, etc. (useless information for someone using the solution).
Your solutions should be computer generated (not hand sketched like they
currently are).
Your solutions should be excellent and helpful for somebody doing
self-study since you already have a solution. However, the solution shouldnt
be too long.
LB 1, 7, 13 (Check 3 and 9)
SB 2, 8 (Check 4 and 10)
CG 3, 9 (Check 5 and 11)
QH 4, 10 (Check 6 and 12)
AJ 5, 11 (Check 7 and 13)
JW 6, 12 (Check 1, 2, and 8)
Midterm Monday, Oct. 26, open book and closed notes covering chapters
8, 25, and 26
HW#5 due Monday, Oct. 19, A26.6-A26.10
HW#4 due Monday, Oct. 12, A26.1-A26.5
HW#3 due Wednesday, September 23,
A8.10-A8.14, A20.31
HW#2 due Monday, September 14, A8.5-A8.8
HW#1 due
Monday, August 31, A8.1-A8.4
Project
2 due Dec. 7
LB
make the Cadence files for Ch. 30
QH
make the Electric file for Ch. 30
The
following solutions are counting for the second project so they should be
excellent, not too long but very clear and informative.
CG
make up solutions for Ch. 30 problems: 1, 5, 12, 13, 20, 21, and 25
SB
make up solutions for Ch. 30 problems: 2, 6, 11, 14, 19, and 22
JW
make up solutions for Ch. 30 problems: 3, 7, 10, 15, 18, and 23
AJ
make up solutions for Ch. 30 problems: 4, 8, 9, 16, 17, and 24
Project 1 due Oct. 5. Using the 50 nm CMOS process
from the book with a VDD of 1 V design the lowest-noise op-amp possible with
the following specifications:
· DC open-loop gain greater than 80 dB when driving a 1k resistor
· Unity-gain frequency greater than 100 MHz when unloaded or driving a 1k resistor, 10 pF capacitor, or the parallel combination of a 1k and 10 pF
· CMRR > 60 dB from DC to 1 MHz
· Input CMR from 400 mV to 800 mV
· Output swing when driving 1k from 100 to 900 mV
· Systematic offset < 10 mV
· Power dissipation < 1 mW when the op-amp is in the follower configuration driving a 1k load with an input voltage of 500 mV.
Please submit this project to me via email. Attach your LTspice simulation directory zipped-up and your report, less than 20 pages, in PDF format. Your report should discuss your design (the topology, design considerations, trade-offs, etc.) and thoroughly characterize the performance of the op-amp (noise, gain, VOS, CMRR, PSRR, THD, etc.) In your reports summary comment on the performance of your design compared to the LT1364 bipolar high-speed op-amp discussed in Ch. 8.