**Homework
assignments for ECE 614 Advanced Analog IC Design, Spring 2008**

Homework
guidelines are found here.

**HW15 ** due Wednesday, May
7, using LTspice and
ideal components, simulate the operation of a 4-bit SAR charge
redistribution
ADC clocked at 100 MHz.
Show how the ADC operates
using an ideal 4-bit DAC to reconstruct the ADCs input. Zip up your
simulations and email them to me (nothing else should be turned in).

**HW14** due Wednesday,
April 30, A29.4

**HW13** due Wednesday,
April 23, A29.1, A29.2,
and A29.3

**HW12** due Wednesday,
April 16, A27.6, A28.7,
A28.8, and A28.9

**HW11 ** due Monday, April 7,
A27.1 and A27.2

**HW10** due Wednesday,
March 12, A26.1 A26.5

**HW9 ** due Wednesday, March
5, A25.6

**HW8** due Wednesday,
February 27, A25.5

**HW7** due Monday,
February 25, A25.1 and A25.2

**HW6** due Wednesday,
February 13, A9.21,
A9.22, A20.31

**HW5** due Monday,
February 11, A8.14 and A8.15

**HW4** due Wednesday,
February 6, A8.10 and
A8.13

**HW3** due Monday,
February 4, A8.8 and A8.9

**HW2 ** due Wednesday,
January 30, A8.4 and A8.5

**HW1** due Monday, January
28, A8.1, A8.2, A8.3

**Proj2 **- Each student will
prepare and give a 30
minute tutorial presentation, with 5 minutes for questions, to the
class on the
topics seen below. The instructor and 3 students in the class will
grade the
students presentation based on: the quality and clarity of the
information
presented and the students answers to questions. Since the
presentations only
last 30 minutes some thought will need to be put into ensuring the
presentation
time is well utilized. Power point presentations can be used and the
presentations will be recorded.

·
An
the design of sigma-delta sensing circuits for sensing in multi-level
resistive
memory, April 23

·
Ba
an overview of extracting parasitics in an integrated circuit from a
CAD tool
perspective, April 23

·
Bu
design and operation of the successive approximation ADC, April 28

·
Fi
design and operation of the pipeline ADC, April 28

·
Gu
design and operation of the W-2W DAC and its application to programming
resistive memory, April 30

·
Ha
design of crystal oscillator circuits in CMOS, April 30

·
Li
design and operation of folding ADCs, May 5

·
Ne
design and operation of delta-sigma ADCs, May 5

·

·
Zh
design and operation of charge-scaling DACs, May 7

**Proj1** due in several
parts.

Part 4 due
Wednesday, March 5, summarize the problems associated with RTS noise in
Flash
memory. Suggest direction(s) to focus on for future Flash memory parts.
Provide
supporting comments and evidence for your suggestions. Please limit
this
summary to 4 pages.

Part 3 due
Wednesday, February 27, show, using LTspice simulations, sensing in
Flash
memory using delta-sigma modulation and using the more traditional
techniques
(the Flash cell discharges the bitline capacitance and a comparator, or
comparators, are used to determine if the voltage on the bitline is
above or
below a reference value). Again, keep your results to less than 4
pages. Make
sure what you turn in indicates you understand the operation of the two
sensing
circuits.

Part 2 due
Monday, February 25, compare the SNR you got in Part 1 to what you get
just by
looking at the time-domain noise currents seen in Fig. 2 of the Kurata paper. Comment on the
comparison. For slow noise
variations will delta-sigma modulation help with sensing? Why or why
not? Note
your answer should discuss sensing over short periods of time and over
long
periods. Finally, using LTspice, show how you can model 1/f, 1/f^2, and
RTS
noise. Please keep what your analysis and simulation results to 4 pages
or
less.

Part 1 due
Wednesday, February 20, compare the SNR we get using traditional
sensing
techniques in Flash memory (Flash cell current discharging the bit line
capacitance, integrating the signal and noise) to those we get using
delta-sigma modulation (see Ch. 17, no integration of the noise). Use
the
experimental data from the Kurata
paper to provide
numbers in your analysis. Assume the bit line capacitance is 5 pF for a
read
current of 100 nA. Please keep your analysis to 4 pages or less.