ECE 615 CMOS Mixed-Signal IC Design

Homework assignments and Project Information for ECE 615 CMOS Mixed-Signal IC Design, Spring 2009

Homework guidelines are found here.

Send MS word files to me with your name on the solutions before class starts on the date HW is due.
Include problem statement and write solutions in a tutorial fashion with the goal of teaching.
Make the solution as easy to understand as possible while providing additional, helpful, information like simulation netlists or results.
Name your files with the problem number, 2.1.doc, 2.2.doc, etc. Each problem solution should be in its own file.

HW10 – due Monday, May 4, Kaijun-9.10 and 9.11, Geng-9.5 and 9.12 (the new one, see errata, which is the old 9.13), Avi-9.1, Lincoln-9.2, Durand-9.3, Shantanu-9.4, Qawi-9.6 and 9.9, Hari-9.7 and 9.8

HW9 – due Wednesday, April 29, Kaijun-8.1, Shantanu-8.10, Avi -8.2, Lincoln-8.3, Durand-8.4, Jake-8.5, Qawi-8.7, Hari-8.6, Geng-8.9

HW8 – due Monday, April 20, Lincoln-7.4, 7.7, 7.8, 7.35, 7.36, and 7.37, Durand-7.6, 7.11, and 7.34, Jake-7.5, 7.9, 7.10, 7.29, 7.31, 7.32, 7.33, 7.38, and 7.39, Qawi-7.3, 7.12, 7.27, 7.28, 7.30, and 7.41, Kaijun-7.2, 7.13, 7.25, and 7.26, Avi-7.1, 7.14, 7.23, 7.24, and 7.40, Hari-7.15, 7.20, 7.21, and 7.22, Geng-7.16, 7.17, 7.18, and 7.19, Shantanu-8.8, and 8.11.

HW7 – due Wednesday, April 8, Lincoln-3.5, Durand-3.12, George-3.13, Tyler-3.14, Qawi-3.15, Kaijun-3.16, Avi-3.17, Hari-3.18 and 6.7, Geng-3.19 and 3.20

HW6 – due Wednesday, March 18, Lincoln-6.1 and 3.1 and 3.11, Durand- 6.2, Shantanu- 6.3 and 6.9 and 3.7, Tyler-6.4 and 6.8 and 3.10, Qawi-6.5 and 3.2 and 3.9, Kaijun-6.6 and 3.8, Avi-6.11, Hari-6.10 and 3.3 and 3.6, Mouli-6.7 and 3.5, Geng-6.12 and 3.4

HW5 – due Wednesday, March 11, Lincoln-4.19, Durand-4.20 and 5.10, Shantanu-4.21, Tyler-4.22, Qawi-5.5, Kaijun-5.6, Avi-5.8 and 5.11, Hari-5.9, Mouli-4.17, Geng-4.18 and 5.12

HW4 – due Wednesday, March 4, Lincoln-4.12, Durand-4.1, Shantanu-4.2, Tyler-4.3, Qawi-5.1, Kaijun-5.7, Avi-5.3, Hari-5.4, Mouli-4.4 and 4.5, Geng-5.2

HW3 – due Wednesday, February 25, Lincoln-4.8, Durand-4.9, Shantanu-4.10, Tyler-4.11, Qawi-4.13, Kaijun-4.14, Avi-4.15, Hari-4.17, Mouli-4.6, Geng-4.7

HW2 – due Wednesday, February 18, Lincoln-2.5, Durand-2.1 and 2.6, Shantanu-2.7, Tyler-2.8, Qawi-2.9, Kaijun-2.10 and 2.18, Avi-2.11 and 2.17, Ramya-2.12 and 2.16, Hari-2.2 and 2.13, Mouli -2.3 and 2.14, Geng-2.4 and 2.15

HW1 – due Wednesday, January 28, Lincoln-1.1and 1.11, Durand-1.7 and 1.17, Shantanu-1.2 and1.12, Tyler-1.3 and 1.13, Qawi-1.4 and 1.14, Kaijun-1.5 and 1.15, Avi-1.6 and 1.16, Hari-1.8, Mouli -1.9, Geng-1.10

Proj2 – due Wednesday, May 6, design, layout, and simulate a second-order Delta-Sigma modulator using switched capacitors in AMI’s C5 process. The off-chip inputs to your circuit are Vin+, Vin-, VCM, and clock (generate non-overlapping clock signals on-chip). The off-chip output is the 1-bit output of your DS modulator. Use MATLAB for processing (filtering and decimation) this output. Email me, before 6:30 PM on May 6, a PDF of your report detailing the design considerations, discussions concerning trade-offs, summary of the performance based on simulations, and a jelib containing the schematics and layouts that are LVS and DRC clean.

Proj1 – due Monday, April 6, develop the theory of operation for the passive second-order NS modulator seen in Fig. 6.17 using K-paths, Fig. 6.24, with the added amplifier seen in Fig. 6.24 to reduce the effects of comparator offsets and clock jitter (assume G = 10). Use your results to design an 8-path modulator clocked at 100 MHz. Assume a VDD of 1 V and use all ideal components already available in the LTspice examples from the book. Show how the modulator/filter’s SNR (the ADC’s SNR) can be traded-off for conversion bandwidth using MATLAB interfaced with LTspice output from your modulator design. Your detailed report in PDF format should be emailed to me before class starts on April 1.

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