ECG 721

Homework assignments and Project Information for ECG 721 Memory Circuit Design, Fall 2015

Homework guidelines are found here.
Note that an A in front of the problem indicates an additional problem from the book’s webpage, not a problem from the book’s end–of–chapter problems.

HW#18 – A19.10 and A19.11, due Wednesday, November 4

HW#17 – A19.2 and A19.3, due Monday, November 2

HW#16 – A19.8 and A19.9, due Wednesday, October 28

HW#15 – A19.6 and A19.7, due Monday, October 26

HW#14 – A18.5, due Wednesday, October 14

HW#13 – A18.4, due Monday, October 12

HW#12 – A18.1 and A18.2, due Wednesday, October 7

HW#11 – A17.3, due Monday, October 5

HW#10 – A17.2 and A17.4, due Wednesday, September 30

HW#9 – A17.1, due Monday, September 28

HW#8 – A16.14 and A16.15, due Wenesday, September 23

HW#7 – A16.12, due Monday, September 21

HW#6 – A16.9–A16.10, due Wednesday, September 16

HW#5 – A16.6–A16.8, due Monday, September 14

HW#4 – A16.4 and A16.5, due Wednesday, September 9

HW#3 – A16.1–A16.3, due Wednesday, September 2

HW#2 – A11.1, A11.10, and A11.11, due Monday, August 31

HW#1 – A10.1–A10.3, due Wednesday, August 26

Projects –

Grade will be based on a presentation at the end of the semester to the class.
Your presentation should be in ppt and tutorial in nature (to teach the class).
I would like to record the presentation and post your ppt in PDF format online (if this is a problem please let me know)
Presentation length is 60 minutes with and additional 5 minutes for questions

YL – design of all digital DLLs for use in SDRAM (include tutorial operation of SDRAM followed by why a DLL is needed in an SDRAM) – November 18

KB – the use and design of synchronous mirror delays (what they are and how they work) – November 25

ML – use of an over–damped PLL in place of DLL in SDRAM. Is this possible or practical? What are the benefits and drawbacks? – November 23

WW – the use of self–biasing in the design of PLLs and DLLs – November 16

AR – design of analog PLLs, a tutorial overview – November 30