Homework assignments and Project Information for EE 420 Engineering Electronics II and ECG 620 Analog IC Design, Spring 2016

• Homework guidelines are found here.
• Note that an A in front of the problem indicates an additional problem from the book’s webpage, not a problem from the book’s end–of–chapter problems.

HW#13 – A24.1–A24.3, due Tuesday, April 26

HW#12 – A22.13 and A23.5–A23.6, due Tuesday, April 19  

HW#11 – A22.2, A22.3, and A22.9, due Tuesday, April 12   

HW#10 – A1.4, A1.5, A21.14, A21.19, and A21.25, due Tuesday, April 5

HW#9 – A21.5–A21.11, due Tuesday, March 29

HW#8 – A21.1–A21.3, due Tuesday, March 15   

HW#7 – A20.21–A20.24, due Tuesday, March 8

HW#6 – A20.11, A20.12, A20.15, and A20.17, due Tuesday, March 1

HW#5 – A20.1–A20.6, due Tuesday, February 23

HW#4 – A9.2, A9.5, A9.11, and A9.29, due Tuesday, February 16 

HW#3 – Book problems 9.13 (but change the 1.3 V to 1.15 V), 9.14 (but change the 40 uA to 20 uA), 9.23 (but use 10/2 [= 500n/100n = 0.5u/0.1u] devices for both the PMOS and NMOS), 9.26 (and verify your answer using LTspice), due Tuesday, February 9

HW#2 – Book problems 9.6 and 9.8–9.12, due Tuesday, February 2

HW#1 – Book problems 9.1 (but change the 2 V to 3 V), 9.3 (but change the 100k to 50k), 9.5 (but change the 3 V to 1.5 V), and 9.7 (no modifications), due Tuesday, January 26

Course project – using On's C5 process (process information can be found at On's website, minimum L is 600 nm, SPICE models are found in C5_models.txt) design a voltage follower using an op–amp (input voltage connected to the noninverting, "+," input of the op–amp and output voltage connected back to the inverting, "–," input of the op–amp) that can operate with a VDD between 3 and 5 V while driving a 10 pF (max) and 1k (min) load. 

Other requirements are:

• The error (difference) between the input signal and output signal should be < 0.1%  
• Bandwidth of the follower should be > 100 MHz
• Slew–rate with maximum load > 100V/microsecond
• Current draw from VDD should be less than 10 mA under full load conditions
  
• Output swing should be 80% of VDD (e.g. 0.5 V to 4.5 V when VDD = 5 V or 0.12 V to 2.88 V when VDD = 3 V. The output swing doesn't have to be centered as these examples are, that is, 0.25 to 4.25 V when VDD = 5 V is fine too).
  

Your report should contain, at least, the following:

• Simulations showing large– and small–signal operation including AC response
• Show operation, including settling time and slewing, with no load and varying loads
• Your detailed design considerations
• Show schematics with a comparison between hand calculations and simulations along with comments 
• A table summarizing results such as input CMR as a function of VDD, unity–gain frequency, power, slew–rate, CMRR, PSRR, output swing as a function of VDD, etc.

This is not a team effort. A significant portion of your grade will be based on your report. Your report, and a zipped up folder of simulations, is due, via email to rjacobbaker@gmail.com, at the beginning of class on Tuesday, May 3. Projects received at 10:01 AM or later on May 3 will receive a 0 so take the deadline seriously. 

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