Homework assignments and Project Information for EE 420 Engineering Electronics II and ECG 620 Analog IC Design, Spring 2020

• Homework guidelines are found here.  

HW#19 – hw19.pdf, due Monday, April 27, Lecture 23
HW#18 – hw18.pdf, due Monday, April 20, Lecture 21
HW#17 – hw17.pdf, due Wednesday, April 15, Lecture 20
HW#16 – hw16.pdf, due Monday, April 13, Lecture 19
HW#15 – hw15.pdf, due Monday, April 6, Lecture 18
HW#14 – hw14.pdf, due Wednesday, April 1, Lecture 17
HW#13 – hw13.pdf, due Monday, March 30, Lecture 16  
HW#12 – hw12.pdf, due Wednesday, March 25, Lecture 15
HW#11 – hw11.pdf, due Monday, March 9, Lecture 13
HW#10 – hw10.pdf, due Wednesday, March 4, Lecture 12
no hw due on Monday, March 2
HW#9 – hw9.pdf, due Wednesday, February 26, Lecture 10
HW#8 – hw8.pdf, due Monday, February 24, Lecture 9
HW#7 – hw7.pdf, due Wednesday, February 19, Lecture 8  
HW#6 – hw6.pdf, due Wednesday, February 12, Lecture 7  
HW#5 – hw5.pdf, due Monday, February 10, Lecture 6  
HW#4 – hw4.pdf, due Wednesday, February 5, Lecture 5  
HW#3 – hw3.pdf, due Monday, February 3, Lecture 4  
HW#2 – hw2.pdf, due Wednesday, January 29, Lecture 3  
HW#1 – hw1.pdf, due Monday, January 27, Lecture 2 

Course project - using On Semiconductor's 500 nm process (C5 with two polysilicon layers and 3 levels of metal with a lambda of 300 nm) design an op-amp that can operate with a VDD down to 3 V while driving 1,000 pF (max) and 100 (min) load. The MOSIS information for this process is located here and the SPICE models are C5_models.txt (of course you should characterize your design with no load and other loads to show that it still meets specifcations).

Other requirements are:

• DC open-loop gain > 60 dB (80 dB for students taking ECG 620) under all load and VDD condition
• Gain-bandwidth product should be > 5 MHz  
• Slew-rate with maximum load > 1V/microsecond
• Quiescent current draw should be less than 2 mA with no load
  

Your report should detail your design considerations, simulation schematics with results, and provide a table summarizing the results (input CMR as a function of VDD, unity gain frequency, power, slew-rate, etc.) This is not a team effort. A significant portion of your grade will be based on your report and your power consumption. 

I should receive the PDF of the electronic report and a zipped–up directory of your design via email (r.jacob.baker@unlv.edu) before 4 pm on Wednesday, May 6, 2020. Receiving the project via email at 4:01 pm, as indicated in my email mailbox, or later will result in a 0.  

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