Homework assignments and Project Information for EE 421 Digital Electronics and ECG 621 Digital Integrated Circuit Design, Fall 2013

• Homework guidelines are found here.
• Note that an A in front of the problem indicates an additional problem from the book’s webpage, not a problem from the book’s end–of–chapter problems.
• All layouts and schematics should be drawn using Electric. 
• Simulations should be performed using LTspice from schematics generated using Electric.
• Drawing schematics using LTspice will result in zero credit.
  

HW#18 – A13.3–A13.4, and A14.1, due Wednesday, November 27

HW#17 – A12.4 and A13.1, due Monday, November 25

HW#16 – A12.1 and A12.3, due Wednesday, November 20

HW#15 – A11.4, A11.6, A11.10, and A11.11, due Monday, November 18

HW#14 – A10.7, A10.9, and A11.1–A11.2, due Wednesday, November 13

HW#13 – A10.3–A10.4, due Wednesday, November 6

HW#12 – A10.1–A10.2, due Monday, November 4

HW#11 – A6.13–A6.16, and A6.19, due Wednesday, October 16

HW#10 – A6.9, A6.11, and A6.12 due Monday, October 14

HW#9 – A6.4–A6.6, due Wednesday, October 9

HW#8 – A6.2–A6.3, due Monday, October 7

HW#7 – A5.1–A5.2, A5.4, A5.7, due Wednesday, October 2

HW#6 – A4.1–A4.6, due Monday, September 30

HW#5 – A3.4–A3.5, A3.7–A3.8, and A3.10, due Wednesday, September 18

HW#4 – A1.11 and A3.1–A3.3, due Monday, September 16

HW#3 – A1.8–A1.10 and A2.5–A2.6, due Wednesday, September 11

HW#2 – A1.6–A1.7, A2.1, A2.2, and A2.4, due Monday, September 9

HW#1 – A1.1–A1.5, due Wednesday, September 4

Course projects – Read the policy on the course webpage concerning turning in late work. These projects are NOT group efforts. What you turn in should be your own work. I will ask my TA for help in looking for layouts that are common in two project jelib files (so do your own work!)

Your project reports should detail:

• The reasons for the topology you selected including design considerations
• Hand calculations with comparisons to simulations 
• A pin diagram for the layout (how to connect the layout to bond pads if we fabricate the design)
• Clear layout documentation (zoomed in and outlines of the layout for easy grading).
• Layout should be easy to understand (orderly and labeled). While tight layouts are desirable it's more important to provide clear layouts.
• Email me your (clean) Jelib file and project report in PDF or Word formats.
• I should be able to figure out what to simulate and how to simulate it without any effort (make sure this is very clear!) 
• I will have the MOSFET models in C:\Electric\C5_models.txt
• I’ll perform an LVS and a DRC on what you send (so make sure everything is clean before emailing me!)
• I should receive the electronic report and jelib via email (r.jacob.baker@unlv.edu) prior to the beginning of class (4 pm) on Monday December 2, 2013.

EE 421/ECG 621 project –

1. In EE421_ECG621_f13_proj.jelib is a bandgap reference schematic. A bandgap is a common circuit used for generating a voltage reference of approximately 1.25 V that doesn’t change [much] with temperature and VDD variations. The first part of the project, for both ECG 621 and EE 421, is to layout this bandgap. Note that I’ve already laid out the parasitic pnp device (the diode). Make sure you simulate the operation of the bandgap and can show the minimum VDD that the bandgap can have while still maintaining a 1.25 V output voltage (say to within +/– 25 mV or so). Note that the icon for the bandgapreference has 3 pins: vdd, gnd, Vref. Also note that Vref can’t supply current (it can only be connected to the gates of MOSFETs).
2. The second part of the project for both ECG 621 and EE 421, is to design a circuit that senses an input voltage (you should use the bandgap from part 1 in this circuit). The output of the circuit is a logic 1 (vdd) when the input is less than 15 V and a logic 0 (ground) when the input is greater than 15 V. The circuit’s input should draw no more than 10 uA of current and no less than 1 uA of current. The sensing circuit you design should have a built in hysteresis of at least 200 mV (but less than 500 mV). What this means, for 200 mV hysteresis, is that the output of circuit may go high when the input drops to 14.9 V and then low when the input goes beyond 15.1. This is the same thing found in a thermostat controlling your home’s heater. If you have your thermostat set at 70 degrees your heater may kick on when the temperature drops to 69 and then shut off when the house heats up to 71. This keeps the heater from cycling on and off. Characterize your design for VDD ranging from 4 to 5 V and for temperatures ranging from 0 to 100C. Note that your simulations use an icon of your total circuit (what you’ve designed and the bandgap reference) having 4 pins: vdd, gnd, Vin, and Enable out.
3. For ECG 621 only use your design from part 2 to enable a ring oscillator that drives buffers that drive a charge pump that supplies 15 V +/– 250 mV with load currents ranging from 0 to 100 uA (the output of the charge pump is the input in part 2). Again characterize your design for vdd ranging from 4 to 5 V and for temperatures ranging from 0 to 100C. The final cell that I simulate should have vdd and ground inputs with a 15 V output voltage (in other words your final design with everything should be an icon with 3 pins, vdd, gnd, and the 15V output). Note that in SPICE you can model the load current with a current pulse. Show how robust your design is for varying load currents (say a pulse from 0 to 100 uA or from 100 uA to 0 etc.) Some thought is required to demonstrate, via simulations, a robust design. I would also like you discuss the efficiency of the design. Ideally all of the power supplied by vdd, vdd*AVG(I(vdd)), is equal to the power delivered to the load, VLOAD*ILOAD (see page 4 here). In a real circuit this won’t be the case since your circuit will dissipate power.

• This efficiency calculation assumes that Vout, VDD, and Iload are DC values. Make sure only steady-state (no start-up waveforms) are present in I(VDD) when you use the calculator (see link below for help) to calculate the average else your calculations will be incorrect. For example, to ensure that no start-up waveforms are present in the waveforms you may use .tran 50u 200u (a 200u simulation that starts saving data at 50u, again an example).

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