Homework assignments and Project Information for EE 421 Digital Electronics and ECG 621 Digital Integrated Circuit Design, Fall 2016

• Homework guidelines are found here.
• Note that an A in front of the problem indicates an additional problem from the book’s webpage, not a problem from the book’s end–of–chapter problems.
• All simulations, schematics, and layouts should be done using Cadence. Using other tools will result in zero credit.
• Follow the instructions for running an Xterm found here (video)

HW#23 – Show, using simulations, that the sense amplifier in Fig. 16.32 can fail (sensitivity gets poorer or it fails to operate properly) if the input voltages are too high or too low, due Wednesday, December 7
HW#22 – A14.1 and A14.3, due Monday, December 5
HW#21 – A13.1 and A13.6, due Wednesday, November 30
No HW assigned, and thus due, on Monday, November 28
HW#20 – A13.1 and A13.2, due Wednesday, November 23
HW#19 – A12.1 and A12.5, due Monday, November 21
HW#18 – A11.11,  due Wednesday, November 16.
HW#17 – A11.1–A11.2 (but use the C5 process, again, scale = 600 nm) and layout a 25–stage ring oscillator using 12u/0.6um PMOS and 6u/0.6u NMOS. Turn in a concise schematic and the layout with indication of passing DRC and LVS. Due Monday, November 14.
HW#16 – A10.4 but use the C5 process with a scale factor of 0.6 um (a 10/1 device is 6um/0.6um). Also, in your own words describe an inverter's voltage transfer curve including how the beta ratio influences switching point, VOH, VOL, NMH, and NML. What is the ideal switching point voltage and ideal voltage transfer curve for an inverter? Due Monday, November 7.
HW#15 – Using the C5 proces with 3/0.6 devices work A10.9. Estimate the delay, in the C5 process, of a 6/0.6 PMOS and NMOS charging/discharging a 1 pF capacitor. Verify your answer with SPICE (Spectre). Due Wednesday, November 2.
HW#14 – A10.1–A10.3 but use the C5 process with 6/0.6 devices. Due Monday, October 31.
HW#13 – A bandgap reference circuit is a circuit that generates a reference voltage that doesn't vary (much) with changes in power supply voltage and temperature. For the course projects we'll use the bandgap circuit, designed for the C5 process, found in bandgap.zip. For HW#13, run the simulations found in this design directory and comment to show that you understand what the simulations show, that is, the circuit's limitations (e.g., how low can the power supply go before the bandgap output voltage drops? how much does the reference voltage change with temperature? how does the diode's voltage change with temperature, how much current does the bandgap circuit draw?, etc.). Turn in these simulation plots with comments at the beginning of class on Wednesday, October 26. In addition to this, lay out the bandgap reference circuit, again, for use in your course projects, making sure that your layout DRCs and LVSs without errors. Email your zipped–up bandgap directory (don't change the name, that is, it should still be "bandgap.zip"), now with the layout of the bandgap, to the course TA for grading (so she can determine if your layout DRCs and LVSs) before the beginning of class on Wednesday, October 26.
HW#12 – A6.10–A6.15.  Due Wednesday, October 12.
HW#11 – A6.9, and suppose an RC circuit is formed using a 30 um x 30 um NMOS device in the C5 process and a 100k resistor, see the topology in Fig. 6.20 of the book. If the MOSFET is biased in strong inversion with a DC voltage source estimate the resulting circuit's 3–dB frequency. Show your estimate is correct using an AC simulation (frequency on the x–axis). Then, using a transient simulation (time on the x–axis), show that a small–amplitude input sinewave at the 3–dB frequency will result in a output sinewave at 0.707 times the amplitude. Due Monday, October 10.
HW#10 – A6.5, A6.6, and layout, DRC, and LVS NMOS devices having a W/L of 3u/9u and 90u/0.6u (with 5 fingers). Due Wednesday, October 5.
HW#9 – A5.4, A6.2, generate a schematic for the RC circuit show in Fig. 1.24 having pins Vin and Vout. Using a symbol view for this schematic simulate the operation of the circuit as seen in Fig. 1.24. Using a poly1 resistor and a poly–poly capacitor lay out this circuit. DRC and LVS your design. Finally, generate IV plots (ID v. VSG and VGS, and ID v. VSD and VDS for varying VSG and VGS) for both the NMOS and PMOS devices in the C5 process sized 6u/0.6u (= W/L). Due Monday, October 3.
HW#8 – A4.5 and layout, DRC, and LVS a 2 pF poly–poly capacitor and a 10k resistor using poly2 (elec) using the hi–res mask (to block the doping of poly2 so it's sheet resistance is high). Use the LVS tool to determine the sheet resistance of hi–res poly2. Show your hand calculations for determining the size of the capacitor and resistor. Due Wednesday, September 28.
HW#7 – A3.10, A4.1, A4.4, and layout a 6u/0.6u (= W/L) NMOS device connected to 4 bond pads. DRC and LVS your layouts (see Tutorial 2 and Tutorial 6).  Due Monday, September 26.
HW#6 – A3.4 and A3.8. Due Wednesday, September 21
HW#5 –  A3.2, A3.5, and layout a (roughly) 1.5 mm x 1.5 mm padframe (1,500 um x 1,500 um) in the C5 process using 75 um square bond pads (see Tutorial 6). Show a schematic and symbol for your padframe. Show the details of your bond pad including a screen shot of the size using the ruler, the glass layer, the metal3 layer, and the pad layer as the outline of the cell. Also show a screen shot of your padframe showing the size using the ruler. Due Monday, September 19.  
HW#4 – A2.5, and then design, layout, and simulate an attenuator circuit, using n–well resistors, that takes a 0 to 5V input signal and generates two outputs, one that goes from 0 to 2.5 and another that goes from 0 to 1 V. In other words, when the input to the circuit is 5V, one output is 2.5V and the other output is 1V. If the input is 2.5V then one output is 1.25 and the other output is 0.5V. Turn in images of: your basic resistive divider schematic, the symbol for your schematic, simulation schematic using the symbol, simulation results, layout of your cell, and images showing DRC and LVS were passed, that is, 7 images on no more than 3 pages. Due Wednesday, September 14  
HW#3 – A2.1, A2.2, and go through Cadence Tutorial 1 but use 20k n–well resistors instead of 10k resistors. Turn in images of: your basic resistive divider schematic, the symbol for your schematic, simulation schematic using the symbol, simulation results, layout of your cell, and images showing DRC and LVS were passed, that is, 7 images on no more than 3 pages. Due, Monday, September 12  
HW#2 – A1.1, A1.3, A1.13, and A1.21 due, Wednesday, September 7  
HW#1 – Sketch, on the same time–domain plot, Vin and Vout for each (two sketches and two sets of hand calculations) of Figs. 1.21 and 1.22 if the capacitor from Vout to ground is increased to 2 uF. Verify your hand calculated answers for each sketch using Cadence simulations. Make sure your hand calculations and comparisons are clear and concise (in other words follow the homework guidelines). Note that the purpose of this homework assignment is to ensure that you can run Cadence and follow the HW guidelines. Due Wednesday, August 31

Course projects – Read the policy on the course webpage concerning turning in late work. These projects are NOT group efforts. What you turn in should be your own work. 

Your project report should detail:

• The reasons for the topology you selected including design considerations
• Hand calculations, where possible, with comparisons to simulations 
• A pin diagram for the design's layout (how to connect the layout to bond pads if we fabricate the design)
• Clear layout documentation (zoomed in and outlines of the layout for easy grading).
• Layout should be easy to understand (orderly and labeled). While tight layouts are desirable it's more important to provide clear layouts.
• Email me your (*clean*) zipped–up design directory (that I can place in my CMOSedu directory) file and project report in PDF format.
• I should be able to figure out what to simulate and how to simulate it without any effort (make sure this is very clear!) 
• I’ll perform an LVS and a DRC on what you send (so make sure everything is clean before emailing me!)
• One common error, that will make you lose a larger number of points, is sending me a directory that isn't self–contained, that is, references a cell in some other directory in your account (that I obviously don't have access to) so I can't simulate your design. 
• I should receive the electronic report and zipped–up directory of your design via email (r.jacob.baker@unlv.edu) prior to the beginning of class (4 pm) on Monday, November 28, 2016. Recieving the project via email at 4:01 pm or later will result in a 0.

EE 421/ECG 621 project – The course project is to design a CMOS switching power supply, a synchronous Buck converter, that is powered with a VDD that can vary from 4 to 5.5 V. The power supply uses an off–chip inductor and capacitor to generate a constant output voltage of 2.5 V, which we'll call Vout below, for load currents ranging from 0 to 100 mA. 

1. In bandgap.zip is a bandgap voltage reference schematic designed for the C5 process. A bandgap is a common circuit used for generating a voltage reference of approximately 1.25 V that doesn’t change [much] with temperature and VDD variations. The first part of this project is lay out this bandgap. You shold have already done this in HW#13. Note that I’ve already laid out the parasitic pnp device (the diode) and there are example layouts, for LVSing, in this zip file. 
2. The second part of the project is to design a circuit that senses an input voltage Vin (this input is connected to the output voltage of the power supply, Vout, for feedback and control). Your design should use the bandgap from part 1. The output (called Enable) of the circuit is a logic 1 (vdd) when Vin is greater than 2.5 V and a logic 0 (ground) when Vin is less than 2.5 V. The circuit’s input, Vin, should draw no more than 50 uA of current and no less than 10 uA of current.  A practical design concern pops–up when Vin is near 2.5 V, which it will be in these projects. What will happen, if the circuit isn't designed correctly, is that the signal Enable will oscillate since Vin is moving slightly above and below 2.5 V. To avoid these oscillations, design your circuit with a small amount of hysteresis.  
• Hysteresis is found in a thermostat controlling your home’s A/C. If you have your thermostat set at 78 degrees your A/C may kick on when the temperature gets to 79 and then shut off when the house cools down to 77 (2 degrees of hysteresis). This keeps the A/C from cycling on and off and thus avoids high–frequency oscillations.
• You need to make an engineering design decision on how much hysteresis is appropriate. You'll see that too much will result in Vin (connected to Vout) varying too much. Too little hysteresis will result in high–frequency oscillations and poor efficiency. Note that you will be able to implement hysteresis by adding delay to the output of this sensing circuit, but hysteresis due to delay won't show up in a DC simulation. You'll see it in a transient simulation.
• Your report, among other things, should show DC sweeps (Vin v. Enable), with varying temperature/VDD, the performance of your design, again with varying temperature/VDD, using transient simulations (not DC simulations). Your design considerations (trade–offs), as mentioned above, should also be concisely detailed. 
• Note that your overall design can't be simulated using a DC simulation because, for proper operation, the output must be switching (hence the name "switching regulator") which can't occur in a DC sweep. Also note that you will likely have to set the output voltage, that is Vout, initial condition to 0. See why and how it was done in Tutorial 5 for ring oscillator so that the feedback circuit oscillates and works properly (in a real circuit noise starts the oscillations, in a simulation we have to help the oscillations start).
  
3. Use your design from part 2, that is, using Enable, to drive buffers (inverters) that enable/disable a PMOS switch connected between VDD and cell's output, out, and an NMOS switch connected between the cell's output, out, and ground. Your report, among other items, should discuss your thoughts on device sizing. Ensure the buffer you design has a lock–out feature, see Fig. 14.9, to ensure that the PMOS and NMOS are never on at the same time to avoid cross–over current.
4. The CMOS synchronous Buck switching power supply you are designing will be connected in 4 places: VDD, gnd, out, and Vout. What you LVS and DRC will be this cell; however, you will need to simulate this cell (generate a symbol view of your final design having 4 pins, or 2 pins if using global vdd! and gnd!) with the off–chip inductor and capacitor (the inductor and capacitor are not part of what we send out for fabrication). The output of your design, out, is connected to the inductor. The other side of the inductor is connected to Vout (the inductor is connected between out and Vout). The capacitor is connected from Vout to ground. Your report should detail your selection of the inductor and capacitor along with simulation results showing performance with varying temperature and power supply (plot your design's efficiency vs load current with different temperatures and power supply voltages). Of course, again, you need to also provide the details indicated above.  Note that efficiency, E, can be calculated using E = (Vout * Iload)/(VDD * AVG(I(VDD))) where AVG(I(VDD)) is the average (see page 4 here) current flowing the power supply, VDD.
• This efficiency calculation assumes that Vout, VDD, and Iload are DC values. Make sure only steady-state (no start-up waveforms) are present in I(VDD) when you use the calculator (see link below for help) to calculate the average else your calculations will be incorrect. For example, to ensure that no start-up waveforms are present in the waveforms you may use .tran 50u 200u (a 200u simulation that starts saving data at 50u, again an example).
5. For students in ECG 621 your design should employ zero–voltage switching (ZVS) to increase efficiency. 
   

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