Homework assignments and Project Information for EE 421 Digital Electronics and ECG 621 Digital Integrated Circuit Design, Fall 2019

• Homework guidelines are found here.
• All simulations, schematics, and layouts should be done using Cadence. Using other tools will result in zero credit.
• Follow the instructions for running an Xterm found here (video).
• All problems are from the book.
• Unless otherwise indicated use the C5 process.
  

HW#18 – 14.16 and 14.21, due Monday, December 2  

HW#17 – 13.10, due Monday, November 18  

HW#16 – 12.11, due Wednesday, November 13  

HW#15 – 11.11, 11.12, and design, layout, and simulate a buffer in the C5 process that uses a 12/6 inverter (minimum lengths) on its input that can drive 10 pF with a reasonable delay (discuss the design and associated trade-offs), due Monday, November 4

HW#14 – 10.6, 10.8, and 10.10, due Monday, October 28

HW#13 - A bandgap reference circuit is a circuit that generates a reference voltage that doesn't vary (much) with changes in power supply voltage and temperature. For the course projects we'll use the bandgap circuit, designed for the C5 process, found in bandgap.zip. For HW#13, run the simulations found in this design directory and comment to show that you understand what the simulations show, that is, the circuit's limitations (e.g., how low can the power supply go before the bandgap output voltage drops? how much does the reference voltage change with temperature? how does the diode's voltage change with temperature, how much current does the bandgap circuit draw?, etc.). Turn in these simulation plots with comments at the beginning of class on Wednesday, October 23. (Do not try to simulate the extracted layouts. The parasitic diodes don't extract properly.) In addition to this, lay out the bandgap reference circuit, again, for use in your course projects, making sure that your layout DRCs and LVSs without errors. Email your zipped–up bandgap directory (don't change the name, that is, it should still be "bandgap.zip"), now with the layout of the bandgap, to the course TA for grading (so he can determine if your layout DRCs and LVSs) before the beginning of class on Wednesday, October 23.  

HW#12 – 6.14, 6.21, 6.24, and 6.27, due Wednesday, October 9    
HW#11 – 6.16-6.18, due Monday, October 7  
HW#10 – 5.8, 5.18, and layout a 2 pF poly-poly capacitor, DRC and LVS your layout, due Wednesday, October 2  
HW#9 – 5.7, 5.10, and layout a 60u/600n NMOS device using 10 fingers, DRC your layout, due Monday, September 30  
HW#8 – 4.14, 4.18, layout a 6u/1.2u PMOS device in the C5 process, and sketch cross-sectional views (at least 3 at various locations) of your layout, due Wednesday, September 25
HW#7 – 3.16, 4.13, layout a 6u/1.2u NMOS device in the C5 process (see Tutorial 2), and sketch cross-sectional views (at least 3 at various locations) of your layout, due Monday, September 23
HW#6 – 3.15 and 3.23, due Wednesday, September 18
HW#5 – 3.13, 3.14, and 3.19 (see Tutorial 6) DRC your layout, due Monday, September 16
HW#4 – 2.19 and 2.22 (verify your answer using Spectre), due Wednesday, September 11 

HW#3 – design, layout, and simulate a 1/3 voltage divider using three 5k n-well resistors in the C5 process (turn in screen shots of your schematic, symbol, simulation using the symbol, and your layout showing that it is DRC and LVS clean), 2.16, due Monday, September 9

HW#2 – 1.19 and 1.20, due Wednesday, September 4 

HW#1 – 1.13-1.15, due Wednesday, August 28

Course projects – Read the policy on the course webpage concerning turning in late work. These projects are NOT group efforts. What you turn in should be your own work. 

Your project report should detail:

• The reasons for the topology you selected including design considerations
• Hand calculations, where possible, with comparisons to simulations 
• A pin diagram for the design's layout (how to connect the layout to bond pads if we fabricate the design)
• Clear layout documentation (zoomed in and outlines of the layout for easy grading).
• Layout should be easy to understand (orderly and labeled). While tight layouts are desirable it's more important to provide clear layouts.
• Email me your (*clean*) zipped–up design directory (that I can place in my CMOSedu directory) file and project report in PDF format.
• I should be able to figure out what to simulate and how to simulate it without any effort (make sure this is very clear!) 
• I’ll perform an LVS and a DRC on what you send (so make sure everything is clean before emailing me!)
• One common error, that will make you lose a larger number of points, is sending me a directory that isn't self–contained, that is, references a cell in some other directory in your account (that I obviously don't have access to) so I can't simulate your design. 
• I should receive the PDF of the electronic report and a zipped–up directory of your design via email (r.jacob.baker@unlv.edu) before 5 pm on Friday, November 29, 2019. Receiving the project via email at 5:01 pm, as indicated in my email mailbox, or later will result in a 0.

EE 421/ECG 621 project – The course project is to design a CMOS switching power supply (SPS), a Boost converter (see Ch. 32), that is powered with a VDD that can vary from 3.75 to 5.25 V. The power supply uses an off–chip Schottky diode, inductor, and capacitor to generate a constant output voltage of 7.5 V, which we'll call Vout below, for load currents ranging from 0 to 20 mA. 

1. In bandgap.zip is a bandgap voltage reference schematic designed for the C5 process. A bandgap is a common circuit used for generating a voltage reference of approximately 1.25 V that doesn’t change [much] with temperature and VDD variations. The first part of this project is lay out this bandgap. You should have already done this in HW#13. Note that I’ve already laid out the parasitic pnp device (the diode) and there are example layouts, for LVSing, in this zip file. 
2. The second part of the project is to design a circuit that senses the output voltage Vout. Your design should use the bandgap from part 1. The output (called Enable) of the circuit is a logic 0 (gnd) when Vout is greater than 7.5 V and a logic 1 (vdd) when Vout is less than 7.5 V. The circuit’s input is connected to Vout and should draw no more than 50 uA of current and no less than 10 uA of current.  A practical design concern pops–up when Vout is near 7.5 V, which it will be in these projects. What will happen, if the circuit isn't designed correctly, is that the signal Enable will oscillate since Vout is moving slightly above and below 7.5 V. To avoid these oscillations, design your circuit with a small amount of hysteresis.  
• Hysteresis is found in a thermostat controlling your home’s A/C. If you have your thermostat set at 75 degrees your A/C may kick on when the temperature gets to 76 and then shut off when the house cools down to 74 (2 degrees of hysteresis). This keeps the A/C from cycling on and off and thus avoids high–frequency oscillations.
• You need to make an engineering design decision on how much hysteresis is appropriate. You'll see that too much will result in Vout varying too much. Too little hysteresis will result in high–frequency oscillations and poor efficiency. Note that you will be able to implement hysteresis by adding delay to the output of this sensing circuit, but hysteresis due to delay won't show up in a DC simulation. You'll see it in a transient simulation.
• Your report, among other things, should show DC sweeps (Vin v. Enable), with varying temperature/VDD, the performance of your design, again with varying temperature/VDD, using transient simulations (not DC simulations). Your design considerations (trade–offs), as mentioned above, should also be concisely detailed. 
• Note that your overall design can't be simulated using a DC simulation because, for proper operation, the output must be switching (hence the name "switching regulator") which can't occur in a DC sweep. Also note that you will likely have to set the output voltage, that is Vout, initial condition to 0. See why and how it was done in Tutorial 5 for ring oscillator so that the feedback circuit oscillates and works properly (in a real circuit noise starts the oscillations, in a simulation we have to help the oscillations start).
  
3. Use your design from part 2, that is, using Enable, to drive buffers (inverters) that enable/disable an NMOS switch connected between ground and the chip's output (which goes to the off-chip inductor and a Schottky diode). Your report, among other items, should discuss your thoughts on device sizing. 
4. Your Boost SPS will be connected in 4 places: VDD, gnd, out, and Vout. What you LVS and DRC will be this cell; however, you will need to simulate this cell (generate a symbol view of your final design having 4 pins, or 2 pins if using global vdd! and gnd!) with the off–chip, Schottky diode, inductor, and capacitor (the diode, inductor, and capacitor are not part of what we send out for fabrication). Your report should detail your selection of the inductor and capacitor along with simulation results showing performance with varying temperature and power supply VDD (plot your design's efficiency vs load current with different temperatures and power supply voltages). Of course, again, you need to also provide the details indicated above.  Note that efficiency, E, can be calculated using E = (Vout * Iload)/(VDD * AVG(I(VDD))) where AVG(I(VDD) is the AVG current supplied by the power supply, VDD (see page 4 here).
• This efficiency calculation assumes that Vout, VDD, and Iload are DC values. Make sure only steady-state (no start-up waveforms) are present in I(VDD) when you use the calculator (see link below for help) to calculate the average else your calculations will be incorrect. For example, to ensure that no start-up waveforms are present in the waveforms you may use .tran 50u 200u (a 200u simulation that starts saving data at 50u, again an example).
5. For students in ECG 621 your design should be able to supply 50 mA of current. 

Some recurring issues with course projects are found at the bottom here (check this for help).

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