Homework assignments and Project Information for EE 421 Digital Electronics and ECG 621 Digital Integrated Circuit Design, Fall 2020

• Homework guidelines are found here.
• All simulations, schematics, and layouts should be done using Cadence. Using other tools will result in zero credit.
• Follow the instructions for running an Xterm found here (video).
• All problems are from the book.
• Unless otherwise indicated use the C5 process.
  

HW#19 – 14.16 but using the C5 process, due Monday, November 23  

HW#18 – 13.11, due Monday, November 16  

HW#17 – 12.11, due Monday, November 9  

HW#16 – design, layout, and simulate (using a symbol view of your oscillator) a 23-stage ring oscillator using C5 giving a comparison between your hand calculations and simulation results. Also design, layout, and simulate (using a symbol view of your NAND gate) a 2-input NAND gate using 10/1 devices in C5 (again, 10/1 = 6u/600n), due Wednesday, November 4

HW#15 – 11.11, 11.12, but using the C5 process. Also, design, layout, and simulate a buffer in the C5 process that uses a 12/6 inverter (minimum lengths) on its input that can drive 10 pF with a reasonable delay (discuss the design and associated trade-offs, use symbol views, that is, don't use transistor views in your simulations), due Wednesday, October 28  

HW#14 – 10.6, 10.7, and 10.8 but using the C5 process (10/1 = 6u/600n), due Monday, October 26

HW#13 - A bandgap reference circuit is a circuit that generates a reference voltage that doesn't vary (much) with changes in power supply voltage and temperature. For the course projects we'll use the bandgap circuit, designed for the C5 process, found in bandgap.zip. For HW#13, run the simulations found in this design directory and comment to show that you understand what the simulations show, that is, the circuit's limitations (e.g., how low can the power supply go before the bandgap output voltage drops? how much does the reference voltage change with temperature? how does the diode's voltage change with temperature, how much current does the bandgap circuit draw?, etc.). Turn in these simulation plots with comments at the beginning of class on Wednesday, October 21. (Do not try to simulate the extracted layouts. The parasitic diodes don't extract properly.) In addition to this, lay out the bandgap reference circuit, again, for use in your course projects, making sure that your layout DRCs and LVSs without errors. Email your zipped–up bandgap directory (don't change the name, that is, it should still be "bandgap.zip"), now with the layout of the bandgap, to the course TA for grading (so he can determine if your layout DRCs and LVSs) before the beginning of class on Wednesday, October 21

HW#12 – 6.21, 6.24, 6.29, and 6.31, due Wednesday, October 7    
HW#11 – 6.1 (but use a 200k resistor), 6.14, 6.17 and layout a 10k resistor using the hi-res layer in C5, DRC and LVS your layout, due Monday, October 5  
HW#10 – 5.8, 5.16, and layout a 1.5 pF poly-poly capacitor, DRC and LVS your layout, due Wednesday, September 30  
HW#9 – 5.7, 5.10, and layout a 60u/0.6u NMOS device using 10 fingers, DRC your layout, due Monday, September 28  
HW#8 – 4.14, 4.18, layout a 12u/0.9u PMOS device in the C5 process, and sketch cross-sectional views (at least 3 at various locations) of your layout, due Wednesday, September 23
HW#7 – 3.22, 4.13, layout a 12u/0.9u NMOS device in the C5 process (see Tutorial 2), and sketch cross-sectional views (at least 3 at various locations) of your layout, due Monday, September 21
HW#6 – 3.16 and 3.24, due Wednesday, September 16
HW#5 – 3.7, 3.14, and 3.19 (see Tutorial 6) DRC your layout, due Monday, September 14
HW#4 – 2.1, 2.16 (but use a sheet resistance of 2k/square), and 2.24, due Wednesday, September 9 

HW#3 – design, layout, and simulate (see Tutorial 1) a 1/3 voltage divider using three 15k n-well resistors in the C5 process (turn in screen shots of your schematic, symbol, simulation using the symbol, and your layout showing that it is DRC and LVS clean), due Wednesday, September 2

HW#2 – 1.18 and 1.22, due Monday, August 31 

HW#1 – 1.13-1.14 (change the 5uA to -10uA), 1.15, due Wednesday, August 26   

EE 421/ECG 621 project is to design a switching power supply (SPS) controller chip for a flyback SPS. 

Flyback SPSs are found in virtually all off-line (from 120V AC) power supplies such as those in USB, phone chargers, laptop supplies, etc. that plug into the wall.

• Your design symbol should have the same footprint as the one seen below so that it can be placed in the simulation to determine if it works correctly.
• Your design is a chip to be used on a printed circuit board with the rest of the components seen below.
• The two DC supplies seen below (170V and 5V) are generated with half-wave rectifiers from the AC line and an additional low voltage tap on the transformer (neither shown below).
• The output of your circuit should be nominally 12.5V and be able to supply well beyond 2A of current to a load. Your design should work with other load currents too including 0, 10mA, 200 mA, etc.
• The controller chip (seen below) in the simulations found in proj_f20.zip use nearly ideal components. You need to design a replacement using real CMOS in C5.
• Your design should use the bandgap voltage reference you laid out in HW#13. This bandgap is used in the design seen below  
• You should sumbit a report characterizing your design, specifically the design considerations and associated schematics, and tables characterizing the behavior (especially power from the 5V supply), clear and concise (!) images of some simulations used to generate the data you entered in your tables. 
• For example, how does your design work at VDD = 4V and temperature of 100C? Characterize your design with changes in temperature and VDD.
  
• Your report should also detail where you think someone trying to improve your design (future work) should focus their time and efforts.  
• Turning in a bunch of images with no coherent associated narrative or just turning in a report with no coherent organization or flow will receive a very low grade (the point is that the design needs to work well, as indicated by simulations, AND your report has to detail the performance of your design and why you did what you did.)
• I should receive the PDF of the electronic report and a zipped–up directory of your design via email (r.jacob.baker@unlv.edu) before 5 pm on Friday, December 4, 2020. Receiving the project via email at 5:01 pm, as indicated in my email mailbox, or later will result in a significant penalty. 

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