Homework assignments for EE 5/410 Spring 2006
Note: off-campus students must turn their homework in via email (using a scanner, word, openoffice, pdf995.com, etc.)
Note: we are using the MOSIS_subm
design rules in this course (minimum length of 2). The book uses cmosedu rules
(minimum length of 1). If a book HW problem specifies a MOSFET of 10/1 (in the
cmosedu rules) we know that this is a MOSFET of 20/2 in the MOSIS rules (the
MOSIS rules use lambda of 300nm in the AMI C5 process while the cmosedu rules
use a scale factor of 600 nm). Note that, for SPICE or layout, both circuits
are equivalent (actual W/L is 6um/0.6um).
Course projects Due Monday May 1. Your project reports should detail the reasons for
the topology you selected, the design considerations, hand calculations with
comparisons to simulations, pin diagram for the layout (how to connect the
layout to bond pads if we fabricate the design), clear layout documentation
(zoomed in and outlines of the layout for easy grading). Please opt for clear
layouts rather than tight layouts. Please email me the TLD files for your
layout and schematic. Make sure your base cell names in the schematic and
layout are clear so I can easily do an LVS. NOTE: I should receive the TLD
files prior to the beginning of class on Monday May 1.
EE 410 project Design a nonoverlapping
clock driver (see the two clock signals in Fig. 14.8) to drive > 1pF loads
(on each output clock) at 100 MHz to >8 V (VDD is 5 V). Ensure that the dead
time in between the rising edges of the clock signal is at least 100 ps.
Characterize your design by output amplitude vs. load capacitance, and dead
time vs. load capacitance. Also, how low can VDD drop in your design while
keeping the output amplitudes above 8 V under full load? What are the
trade-offs? The inputs to your circuit are VDD, GND, and Clock. The outputs of
your circuit are the two phases of the clock signal phi1 and phi2. Note that
the load capacitances are not part of your design (so dont lay them out!) but
they do need to be included in the simulations to model the load the circuit
drives.
EE 510 project Design a voltage generator
that outputs 15 V with a load current from 0 to 5 uA. The circuit inputs are
VDD and ground. Characterize your design, how well does the output stay at 15
V, with changes in VDD, temperature, and load current (both DC and pulsed).
Note that the load current is not part of your design (so dont lay out a resistor
to model a load) but it does need to be included in the simulations.
HW12 Due Monday April 17,
problems A11.8 and A11.9
HW11 Due Monday April 10,
A11.1-A11.3. Layout (use the cells from HW 10 if possible) an inverter using a
20/2 PMOS and a 10/2 NMOS. From both your schematic and layout simulate the DC
transfer curves (see Fig. 11.4, .dc statement using SPICE) and the inherent
propagation delay (without a load, Fig. 11.10, a .tran statement in SPICE).
Show that you can do an LVS between the inverters schematic and layout. Using
your inverter cell (layout and schematics) lay out a 21 stage ring oscillator
(do an LVS). Compare your hand calculations to simulation results.
Midterm2 Monday April 3, on-campus
(for everyone including the video students), in MP201 (same location as last
time) from 12:40 to 1:30 (normal class time). Open book and closed notes (no
photocopies or printouts)
HW10 Due Friday March 24,
online problems A6.8 1, A10.1 2, A10.3 3, A10.5 4, and book problems 6.13 5, 6.14 6, 6.15 7, 10.5 8 (again, please do not copy online solutions), also 9 generate the layout and schematics (and do an LVS) for an inverter (see
Fig. 11.1) made with 20/2 MOSFETs (as always using the MOSIS_subm design
rules). Please submit the problems in the order specified by the red bold
letters.
HW9 Due Wednesday March 15,
online problems A6.4-A.6.7 and book problems 6.1, 6.6-6.10 (please do not copy
online solutions)
HW8 Due Monday March 6,
A6.2-A6.3 (use the MOSIS_subm design rules)
Midterm1 Monday February 27,
on-campus (for everyone including the video students), in the multipurpose
classroom building room MP201 from 12:40 to 1:30 (normal class time). Open book
and closed notes (no photocopies or printouts)
HW7 Due Friday February 24,
A5.1-A5.5, Repeat the layout and schematic example seen in Section 5.4 for both
a 10k n-well resistive divider and 1k polysilicon resistive dividers. Make sure
to show your hand calculations and assumptions (and comments about why X number
of contacts were used, why W width was used, etc.) when selecting resistor
size. Note there should be two schematics and two layouts. Perform an LVS to
show the layouts match the schematics.
HW6 Due Wednesday February 15,
A4.1-A4.7
HW5 Due Friday February 10,
A3.3, A3.4, A3.10
HW4 Due Monday February 6,
A2.5, A3.1-A3.2, A3.7
HW3 Due Wednesday February 1,
A2.6, A2.7, and A2.8
HW2 Due Friday January 27, problems A1.3, A1.4, A1.5 (using WinSPICE), A2.1, and lay out (using LASI) a nominally 50k resistor using n-well with a sheet resistance of 840 ohms/square using the MOSIS submicron (SUBM) rules in our C5, 500 nm process (the lambda is 300 nm). Use minimum allowable n-well width for your layout.
HW1 Due Monday January 23, problems 1.1 1.15.