Homework assignments for EE 5/410 Spring 2007

Note: off-campus students must turn their homework in via email (using a scanner, word, openoffice, pdf995.com, etc.)

Note: we are using the MOSIS_subm design rules in this course (minimum length of 2). The book uses cmosedu rules (minimum length of 1). If a book HW problem specifies a MOSFET of 10/1 (in the cmosedu rules) we know that this is a MOSFET of 20/2 in the MOSIS rules (the MOSIS rules use lambda of 300nm in the AMI C5 process while the cmosedu rules use a scale factor of 600 nm). Note that, for SPICE or layout, both circuits are equivalent (actual W/L is 6um/0.6um).

For these homework problems use the C5 process. (Read this!)

HW11 – Layout and simulate a 23 stage ring oscillator using 30/20 MOSFETs. The only thing I want to get is a (clean!!!) jelib file emailed to me (no paper!) with the transient simulation ready to go (I’ll just press s on the key board and then simulate). The simulation cell should just have the symbol for the ring oscillator with some SPICE code. I likely won’t give partial credit. Due Wednesday April 11.

HW10 – Layout and simulate the operation of two inverters: one sized 30/20 and the other sized 300/200 (note that both use minimum length devices, i.e., L=2). Ensure the layouts are the same height. Estimate using hand calculations, and compare to simulations, the DC switching points of the inverters (two simulations) and their delays driving 100 fF and 5 pF (four more simulations). Email your (clean!!!) jelib file to Dr. Baker. Make sure that all 6 simulations are separate simulation cells in Electric using the symbol for the inverters when grading we can quickly go and create a netlist to check your work. Also, make sure that it’s easy to do an LVS on the two inverters. Due Monday April 9.

HW9 – Verify, using SPICE, that your calculations for the digital models of the MOSFETs in the C5 process are correct. Rework the examples in Ch. 10 using the C5 process (remember that a 10/1 MOSFET from the book is laid out as a 20/2 device using the MOSIS design rules. The scale factor is 300 nm so its actual size is 6 um/0.6um). Due Wednesday April 4.

HW8 – problems A6.4, A6.6, A6.7 use SPICE to display the CV curves (see Fig. 6.4) for 10/1 NMOS and 20/1 PMOS, also draw the schematic, layout, and icon (with the layout DRCed and an LVS performed) the inverter in Fig. 11.1 using 60/2 PMOS and 20/2 NMOS. Due Wednesday March 21.

HW7 – problem 6.1 on page 159. Also, lay out the circuit with pads for probing (note you need 3 pads). Make sure your NCC works correctly, due Monday March 12.

Midterm1 – March 5, closed-book and notes covering Chs. 1-5

HW6 – problems A4.1-A4.3, A5.1-A5.4, A5.7-A5.9 due Wednesday, February 28

HW5 – problems A3.8, A3.11, and A3.12, due Wednesday, February 14

HW4 – problems A2.5, A2.6, A2.8, A2.10, A3.1, A3.2, A3.3, A3.7, due Wednesday, February 7

HW3 – problems A2.3-A2.4, due Wednesday, January 31

HW2 – problems A2.1-A2.2, due Monday, January 29

HW1 – problems A1.6-A1.11, due Wednesday, January 24

Read the policy on the course webpage concerning turning in late work. These projects are NOT group efforts. What you turn in should be your own work. I will ask my TAs for help in looking for layouts that are common in two project jelib files (so do your own work!)

Course projects – Due Monday April 30. Your project reports should detail the reasons for the topology you selected, the design considerations, hand calculations with comparisons to simulations, pin diagram for the layout (how to connect the layout to bond pads if we fabricate the design), clear layout documentation (zoomed in and outlines of the layout for easy grading). Please opt for clear layouts rather than “tight” layouts. Please email me your Jelib file and project report. Please ensure your jelib file is clean (no extra cells in it that aren’t used). I should be able to easily determine the top cell in your layout and schematic. Further, I should be able to figure out what to simulate and how to simulate it without any effort (make sure this is very clear!) I’ll also perform an LVS so double check what you plan on sending prior to sending it. NOTE: I should receive the electronic report and jelib files prior to the beginning of class on Monday April 30.

EE 410 project – Design a nonoverlapping clock driver (see the two clock signals in Fig. 14.8 and the schematic in Fig. 14.9) to drive > 5pF loads (on each output clock) at 100 MHz to >8 V (VDD is 5 V). Ensure that the dead time in between the edges of the two clock signal is at least 100 ps. Characterize your design by output amplitude vs. load capacitance, and dead time vs. load capacitance. Also, how low can VDD drop in your design while keeping the output amplitudes above 8 V under full load? What are the trade-offs? The inputs to your circuit are VDD, GND, and Clock. The outputs of your circuit are the two phases of the clock signal phi1 and phi2. Note that the load capacitances are not part of your design (so don’t lay them out!) but they do need to be included in the simulations to model the load the circuit drives (use SPICE code as you use for specifying VDD and VGND).

EE 510 project – Design a voltage generator that outputs a DC voltage of 15 V (say +/- 300 mV) with a varying load current from 0 to 25 uA. The circuit inputs are VDD and ground. Characterize your design, how well does the output stay at 15 V, with changes in VDD, temperature, and load current (both DC and pulsed). Note that the load current is not part of your design (so don’t lay out a resistor to model a load) but it does need to be included in the simulations with SPICE code (as does VDD and VGND). Current sources using PULSE or PWL sources can be very useful to model the varying load current.

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