Homework assignments for EE 614 Spring 2006
Note: off-campus students must turn their homework in via email (using a scanner, word, openoffice, pdf995.com, etc.)
Final exam Due Monday, May 8 in my office (or mailbox) by 5 pm (students registered for the video section can email
the final to me). Problems A8.15, A8.16, A8.17, A25.5, A25.6, A27.1, A27.2, A27.3, and show how the op-amp designed
in project2 can be used in a pipeline ADC (assume fully differential inputs and outputs) where VREF = VDD. Make sure you
show the gain of 2 (and the associated gain error) and how subtracting 0 or VCM (= VDD/2) from the input prior to the multiply
by 2 works in your circuit.
HW8 Due Wednesday April 26, problems A28.1-A28.10
Project2 Due Wednesday April 12 Design a single-ended to differential-output sample and hold using TSMCs 180 nm
CMOS process. Assume you need to design the circuit for an SNR > 80 dB (how do you determine the required open-loop
gain of the op-amp, the size of the hold capacitors, and the number of bits resolution we can expect?) and a settling time of
less than 5 ns, 100 MHz clock, (how do you determine the gain-bandwidth product of the op-amp?) Characterize your
op-amps performance with offsets (comment on why you picked the offsets you did), variations in VDD (both DC and
noise), and shifts in the capacitor values you selected (say +/- 20%). Finally, using an FFT, look at the THD for your design.
Please keep the report terse and use tables were appropriate (e.g. to summarize the performance of your design).
HW7 Due Wednesday March 22, problems 26.10, 26.14, 26.15, 26.18, 26.19 (again, please show your own work for credit)
HW6 Due Wednesday March 8, problems A26.4-A26.6, also problems from the book: 26.4, 26.7, 26.9,
and 26.17 (please do not copy online solutions)
HW5 Due Monday February 27, problems A26.1-A26.3
Project1 Due Wednesday February 22 Provide a report that details how to design and sense a CMOS active
pixel for low noise performance. Your report should include: a survey of the different types of pixels used in CMOS imagers
including the pros and cons of each, the difference between a PIN diode and a pinned diode (and why one is used over
the other), how and why correlated double sampling (CDS) is used in the pixel, mathematical verification of the comments on
page 506 of the book, and finally examples with simulations of how device sizes affect noise and performance of the pixel
(with the obvious limitation that you cant increase the size of the transistors too much because of limits on the size of the pixel).
Your grade will be based on the clarity of your presentation and the selection of topics you include. Yes, turning in a thick
report with no effort to select relevant material and provide a clear, tutorial like presentation, will ensure a low score.
HW4 Due Wednesday February 8, problems A21.31-A21.33, A22.11, A22.12 (the last homework on noise)
HW3 Due Monday February 6, problems A8.12, A8.13, A8.14, A9.21, A9.22, and A20.31
HW2 Due Monday January 30, problems A8.5-A8.10
HW1 Due Monday January 23, problems A8.1-A8.4