Homework
assignments for EE 615 Fall 2006
Note: off-campus students must turn their homework in via email (using a scanner, word, openoffice, pdf995.com, etc.)
Homework is due at the beginning of the lecture (for all students). Off-campus students should email their HW to the
course TA: Vishal Saxena (send homework to this email address).
The on-campus students should submit their HW before lecture begins
Final exam – Monday, Dec. 11 from 8:15 pm to 10:15 pm
Proj#2 – due Monday, Dec. 4
HW#10 – due Wednesday, Nov. 15, A35.1, A35.2, A35.3, A35.4
Midterm – Monday, Oct. 23, open book, closed notes, covering chapters 30-32
HW#9 – due Wednesday, Oct. 18, A32.4
HW#8 – due Monday, Oct. 16, A32.3
HW#7 – due Wednesday, Oct. 11, A32.1, A32.2
Proj#1 – due Wednesday, Oct. 4
HW#6 – due Wednesday, September 27, A31.4
HW#5 – due Wednesday, September 20, A31.3
HW#4 – due Monday, September 18, A31.2
HW#3 – due Monday, September 11, A30.6, A31.1
HW#2 – due Wednesday, September 6, A30.3-A30.5
HW#1 – due Monday, August 28, A30.1-A30.2
Proj2 You are
tasked with designing a bandpass ADC for a communications chip.
1. The ADC is implemented with a
1-bit fourth-order delta-sigma modulator and digital filter with Vref+ = 1.5 V
(VDD) and Vref- = 0V
2. The system’s clock is 100 MHz
3. The bandpass response is centered
on 25 MHz with a channel BW of 200kHz
4. Use digital I/Q demodulation to
move the information down to DC to 100kHz (and then use a low pass filter to
increase the SNR, that is, remove the modulation noise).
5. Derive the mathematical
description of the ADC (modulator and filter) and the trade-off between filter
complexity and hardware implementation for a given SNR.
6. Use simulations to support your
mathematical derivations. Ensure your understanding is clear in your report.
Note that the project’s goals
are: 1) to show that you understand the concepts (bandpass delta-sigma
modulation, digital filtering, frequency translation (e.g. I/Q demodulation),
using decimation to reduce power, etc.), and 2) to demonstrate your
understanding of the trade-offs involved in the design of this mixed-signal
system (e.g. filter complexity vs. SNR). The goals are NOT to simply get a
working system or to meet some list of design requirements.
As in Proj1 please email your
project to me directly.
Proj1 You are
tasked with designing a bandpass ADC for a communications chip. Here are the
specifications:
1. The ADC is a 4-bit Flash type
with Vref+ = 1.5 V (VDD) and Vref- = 0V
2. The ADC and bandpass filter are
clocked at 100 MHz
3. The bandpass response is centered
on 25 MHz so a comb filter(s) and fs/4 resonator(s) are used
4. The bandwidth of the main lobe
should be fs/8 so K=16 in
the comb filters
5. At least 30 dB attenuation
between the main lobe and the first side lobe
The report should detail: 1) a
mathematical derivation of the ADC/filter’s frequency response, 2) an estimate
for the system’s SNR and thus the final number of bits coming out of the
filter, 3) discussions about how the filter is implemented, aliasing (and the
anti-aliasing filter), how signals outside the passband of interest are
attenuated, etc. 4) detailed and clear SPICE simulations showing proper
operation of the system, 5) simulations showing how you would digitally perform
I/Q demodulation (see Fig. 32.93) and, 6) if decimation may be useful after
demodulation and why.
Please make sure your reports are in
electronic format, and emailed directly to me (not the cmosedu group), presents
figures, discussions, and simulation results in a coherent manner (e.g. turning
in a report where one whole page is a SPICE plot will result in significant
grading penalties.)