EE421L Project

Project - EE 421L Digital Integrated Circuit Design

Author: Matthew Meza

Email: mezam11@unlv.nevada.edu
November 23, 2015

Generating a test chip layout for submission to MOSIS for Fabrication

Pre-lab work

Back-up all of your work from the lab and the course.
Go through Cadence Tutorial 6 seen here.
Read through the lab in its entirety before starting to work on it

Lab Description

In this lab we will design, layout, and simulate a multiple test structures so that they may be fabricated and used
in future labs. There will be seven test structures made in total. Each test structure will have a seperate VDD
supply so that any failed test structures (with shorted vdd to ground) will not affect other test structures.

Lab Requirement

Design of an 8-bit presettable (input "Load") and resettable (input "clear") up/down counter

The outputs of your counter should be buffered before connecting to a pad

A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
NAND and NOR gates using 6/0.6 NMOSs and PMOSs
An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad)

Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit

Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor)
A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)
Whatever else you would like to fabricate to use the remaining pins on the chip
Feel free to "sign" the chip or add a graphic (see the bottom of this webpage). Copy the final, DRC and LVS clean cell you want to fabricate, and then add the graphic since the graphic won't DRC
Also note that you can reduce the number of pins needed by sharing some of them (two resistors, for example, only need 3 pins)

Pre-Lab Excercises

Layout of a single pad!	Symol of a single pad!
Full layout of complete padframe!	Symbol of the complete padframe!

Post-Lab Excercises

25K OHM Resistor - Implemented in N-Well

25K Ohm Resistor schematic	Symbol used for the 25K schematic
Simulation Schematic using the 25k resistor symbol	Simulation of the 25k resistor
Layout View Extracted View	DRC LVS

From the simulation we can see how the different valued capacitor loads affect the delay times and rise/fall times.
The top plot shows the clock in the simulation, the second plot shows the output of the inverter without a capacitive load.
The rest of the plots show the output of the inverter with increasing capacitive load. Notice how the last plots have slower fall/rise time!


                                                                                        Attenuator

Attenuator Schematic	Symbol of Attenuator Schematic
Simulation Schematic for Attenuator	Simulation of the Attenuator
Layout Extracted	DRC LVS

NMOS

6u/.6u NMOS	Symbol for the NMOS device
Simulation schematic of the NMOS device	ID vs VDS with incremental VGS
ID vs VGS with VDS = 0.1 Volts	ID vs VGS with VDS = 5 volts
NMOS Layout	DRC LVS

PMOS

6u/.6u PMOS	Symbol for PMOS
Simulation of PMOS	ID vs VSD with incremental VSG
ID vs VSG with VSD = 0.1 volts	ID vs VSG with VSD = 5 volts
PMOS Layout	DRC LVS

Notice how the curves are mirrored on the X-axis. This is because the current flowing into the drain is plotted!

2u/6u Inverter

12u/6u Inverter	Inverter Symbol
Simulation Schematic of the inverter	Simulation of the inverter
Inverter Layout	DRC LVS

NAND Gate

NAND Gate Schematic using 6u devices	Symbol of the NAND Gate
Simulation Schematic of the NAND Gate	Simulation of the NAND Gate
NAND Layout	DRC LVS

NOR Gate

NOR Gate schematic using 6u Devices	NOR Gate Symbol
NOR Gate Simulation Schematic	NOR Gate Simulation
NOR Layout	DRC LVS

31 Stage Oscillator with Buffer!

Ring Oscillator Schematic	Ring Oscillator Symbol
Buffer for Ring Osc	Buffer Symbol
Ring Osc with Buffer Schematic	Ring Osc with Buffer Symbol
Simulation Schematic of Osc with Buffer	Simulation of the Ring Osc/Buffer with a 20pF Load!
Buffer Layout! Notice the multiple transistors.	Buffer DRC Buffer LVS
Ring Oscillator	Ring Osc DRC Ring Osc LVS

                            8-Bit Resettable, Loadable, Up/Down, Counter

D - Flip Flop	D - Flip Flop Symbol
1-Bit Counter with enable, load input, up/down, and clear!	1-Bit Counter Symbol
8-Bit Counter with enable, load, up/down, and clear!	8-Bit Counter Symbol
Layout of the DFF, Click for larger image DRC and LVS will be shown later	Layout of the 1-Bit Counter, Click for larger image DRC and LVS will be shown later