Lab 4 - EE421L 

Authored by Rhyan Granados

Email: granar1@unlv.nevada.edu

9/16/20

Goal

The objective of this lab is to simulate and observe the IV characteristics of NMOS and PMOS devices in ON's C5 process. Also we will be drafting the layouts for the PMOS and NMOS, and connecting probe pads to various setups of NMOS and PMOS devices.

Prelab

NMOS schematic	NMOS symbol	NMOS in a circuit
NMOS layout	NMOS extracted layout	Simulation Results

PMOS schematic	PMOS symbol	PMOS in a circuit
PMOS layout	PMOS extracted layout	Simulation Results

The Lab

1) Generate 4 schematics and simulations

NMOS ID vs VDS

SCHEMATIC

SIMULATION

SCHEMATIC

SIMULATION

SCHEMATIC

SIMULATION

SCHEMATIC

SIMULATION

2) NMOS and PMOS with 4 probepads attached:layouts , schematics, DRC, and LVS  confirmation

NMOS:

SCHEMATIC

LAYOUTS

DRC

LVS

PMOS:

SCHEMATIC

LAYOUTS

DRC

LVS

File Back-up Proof