Lab 7 - ECE 421L 

Authored by Anthony Peytchev,

Email: peytchev@unlv.nevada.edu

11/01/2023

  

Pre-Lab

Finish Tutorial 5

Schematic:
schem

schem_pe

Symbol:

osc_symb

Layout:

lo_pre

DRC:
drc_pre
LVS:

lvs


Lab 7

Inverter:


Schematic:
inv schem

Symbol:
inv_sym

NAND


Schematic:
nand schem

Symbol:

nand_s

AND

We combined a NAND gate with an Invertor to get this AND gate.
and_s

NOR

nor Schem

Symbol:

nor_s

OR

We combined a NOR with an inverter to get an OR so their respective schematics will be above.

or

Simulation:

Simulation of inverter, nand, and, or and nor:

(Inverter linked to input A)

sim

Sim Schematic for the above.

Sim Schem

2-1 MUX:

Schematic:

schem

Symbol:

21mux_sym

SIM:

sim_mux

Sim Circuit:

mux

Full Adder:

Schematic:

schem

Symbol:

symbol


Backup:

Backed up everything to zip file


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