Homework assignments and Project Information for EE 422/ECG 622 Introduction to Analog IC Design, Spring 2013

• Homework guidelines are found here.
• Note that an A in front of the problem indicates an additional problem from the book’s webpage, not a problem from the book’s end-of-chapter problems.

HW#18 – A24.6, due Monday, April 29

HW#17 – A24.1, due Wednesday, April 24

HW#16 – A22.9, due Monday, April 22

HW#15 – A22.2, A22.3, and A22.4, due Wednesday, April 17

HW#14 – A21.23, A21.24, and A22.1, due Monday, April 15

HW#13 – A21.11, A21.13, A21.19, and A21.22, due Wednesday, April 10

HW#12 – A21.1, A21.3, A21.5, A21.6, and A21.8, due Wednesday, April 3

HW#11 – A20.27-A20.29, due Wednesday, March 20

HW#10 – A20.21, A20.22, A20.25, and A20.26, due Monday, March 18

HW#9 – A20.15, A20.16, A20.17, A20.18, and A20.19, due Wednesday, March 13

HW#8 – A20.1, A20.2, A20.4, A20.6, A20.8, A20.12, and A20.14, due Monday, March 11

HW#7 – A9.15, A9.23, A9.27, and A9.29, due Friday, March 1

HW#6 – A9.14, A9.18, A9.19, A9.20, and A9.30, due Monday, February 25

HW#5 – A9.9, A9.12, and A9.13, due Wednesday, February 13

HW#4 – A9.1 - A9.5, due Monday, February 11

HW#3 – hw3.pdf, due Wednesday, February 6

HW#2 – A6.2, A6.20, and simulate, for both NMOS and PMOS long channel devices discussed in the book I_D v V_DS (or V_SD for the PMOS) at V_GS (or V_SG for the PMOS) = 3 V, due Monday, February 4

HW#1 – hw1.pdf, due Wednesday, January 30

Course projects - using On Semiconductor's 500 nm process (C5 with two polysilicon layers and 3 levels of metal with a lambda of 300 nm so minimum length is 600 nm) design a general purpose op-amp that can operate with 2 V <=VDD <= 6 V while driving 25 pF (max) and 1k (min) load. The MOSIS information for this process is located here and the SPICE models are C5_models.txt

Other requirements are:

DC open-loop gain > 80 dB under all load and VDD conditions

Gain-bandwidth product should be > 10 MHz

CMRR > 90 dB at 100 kHz

PSRR > 90 dB at 100 kHz

Slew-rate with maximum load > 1V/microsecond (those taking EE 422) or 100 V/microsecond (those taking ECG 622)

Your report should detail your design considerations, simulation schematics with results, and provide a table summarizing the results (input CMR as a function of VDD, unity gain frequency, power, slew-rate, etc.) This is not a team effort. A significant portion of your grade will be based on your report. I will grade these reports with you present, that is, you will need to come to my office where we’ll go through your design, simulations, and report.

Your report is due at the beginning of class on Wednesday, May 8. You can bring your SPICE files with you when we meet.

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