ECG 721 Memory
Circuit Design
Spring 2024, University of Nevada, Las
Vegas
Course lecture
notes and videos are located here
Homework
assignments, due dates, and project information are located here
Current
grades are located here.
In this course we will make extensive use of LTspice.
Examples from the lectures are found in ecg721_s24.zip (right click to "Save link as")
Textbook: CMOS Circuit Design, Layout, and Simulation, Fourth Edition (Chapters 16-19) as well as handouts
Instructor: R. Jacob Baker
Teaching Assistant (grader): Abraham Castaneda
Time: offered as an online course to on-campus UNLV students
Course
dates: Wednesday, January 17 to Wednesday, May 1
Location: offered as an online course to on-campus UNLV students
Holidays: Monday, February 19 (Washington's Birthday), March 11 and 13 (Spring break from instruction)
Final exam time: Monday, May 11 from 6 - 8 PM in TBE B-174, open book and closed notes
Course content – A practical introduction to the
transistor-level design of memory circuits. Memory technologies including DRAM,
Flash, MRAM, Glass-based, and SRAM will be discussed.
Prerequisite EE
421 or ECG 621
Grading
25% Midterm - Wednesday, March 6 from 1:00 to 2:15 PM in TBE B-174, open book and closed notes
25% Homework
25%
Course Project
25% Final - a single PDF emailed to Dr. Baker at rjacobbaker@gmail.com before Monday, May 6 at 1 PM