Lecture
notes and videos for EE 421 Digital Electronics and ECG 621 Digital
Integrated Circuit
Design, Fall 2016
December 12 – final exam (comprehensive), 6 to 8 PM, open book and closed notes. (A practice exam is found here.)
December 7 – lec26_ee421_ecg621.pdf and lec26_ee421_ecg621_video – review for the final
December 5 – lec25_ee421_ecg621.pdf and lec25_ee421_ecg621_video – design of clocked comparators for sensing
November 30 – lec24_ee421_ecg621.pdf and lec24_ee421_ecg621_video – memory circuit design
November 28 – lec23_ee421_ecg621.pdf and lec23_ee421_ecg621_video – dyanmic logic gates
November 23 – lec22_ee421_ecg621.pdf and lec22_ee421_ecg621_video – answer project questions and review inverter behaviorNovember 21 – lec21_ee421_ecg621.pdf and lec21_ee421_ecg621_video – review IV characterisitcs of MOSFETs
November 16 – lec20_ee421_ecg621.pdf and lec20_ee421_ecg621_video – clocked circuits, setup and hold times
November 14 – lec19_ee421_ecg621.pdf and lec19_ee421_ecg621_video – answer project questions, power dissipationNovember 7 – lec18_ee421_ecg621.pdf and lec18_ee421_ecg621_video – delay calculations, static logic gate design
November 2 – lec17_ee421_ecg621.pdf and lec17_ee421_ecg621_video – discuss course projects, start ring oscillators and buffers
October 31 – lec16_ee421_ecg621.pdf and lec16_ee421_ecg621_video – the CMOS inverter
October 26 – lec15_ee421_ecg621.pdf and lec15_ee421_ecg621_video – start Ch. 10, models for digital design
October 24 – lec14_ee421_ecg621.pdf and lec14_ee421_ecg621_video – discuss course projects
October 17 – Midterm, open book and closed notes
October 15 – study_session_1.pdf and study_session_1_video – Saturday study session for the midterm
October 12 – lec13_ee421_ecg621.pdf and lec13_ee421_ecg621_video – review for the midterm exam
October 10 – lec12_ee421_ecg621.pdf and lec12_ee421_ecg621_video – subthreshold operation, on/off currents, short-channel behavior
October 5 – lec11_ee421_ecg621.pdf and lec11_ee421_ecg621_video – finish threshold voltage, body effect, MOSFET in the triode and saturation region
October 3 – lec10_ee421_ecg621.pdf and lec10_ee421_ecg621_video – strong inversion, depletion, accumulation, start threshold voltage
September 28 – lec9_ee421_ecg621.pdf and lec9_ee421_ecg621_video – using unit elements for layout of resistors and capacitors, review depletion capacitance again, MOSFET oxide capacitance
September 26 – lec8_ee421_ecg621.pdf and lec8_ee421_ecg621_video – more resistor layout, laying out wide and long MOSFETs, MOSFET capacitances
September 21 – lec7_ee421_ecg621.pdf and lec7_ee421_ecg621_video – more MOSFET layouts, substrate/well contacts, standard cell frames, hi-res poly layer in the C5 process, poly-poly caps
September 19 – lec6_ee421_ecg621.pdf and lec6_ee421_ecg621_video – layout of a MOSFET, the active and poly layers
September 14 – lec5_ee421_ecg621.pdf and lec5_ee421_ecg621_video – delay through the metal layers, crosstalk and ground bounce
September 12 – lec4_ee421_ecg621.pdf and lec4_ee421_ecg621_video – the metal layers, layout out a bond pad, capacitance, vias
September 7 – lec3_ee421_ecg621.pdf and lec3_ee421_ecg621_video – depletion capacitance, RC delay through an n-well resistor, reverse recovery time of a forward biased diode
September 5 – Labor Day Recess
August 31 – lec2_ee421_ecg621.pdf and lec2_ee421_ecg621_video – making a design directory in Cadence for the C5 process, start Ch. 2, The Well
August 29 – lec1_ee421_ecg621.pdf and lec1_ee421_ecg621_video – course introduction, setting up Cadence