Lecture
notes and videos for EE 421 Digital Electronics and ECG 621 Digital
Integrated Circuit
Design, Fall 2019
December 9 – final exam (comprehensive), 6 to 8 PM, open book and closed notes. (A practice exam is found here.)
December 4 – lec27_ee421_ecg621.pdf and lec27_ee421_ecg621_video – review for the final
December 2 – lec26_ee421_ecg621.pdf and lec26_ee421_ecg621_video – introduce memory circuits
November 27 – lec25_ee421_ecg621.pdf and lec25_ee421_ecg621_video – dyanmic logic
November 25 – lec24_ee421_ecg621.pdf and lec24_ee421_ecg621_video – answer even more project questions
November 20 – lec23_ee421_ecg621.pdf and lec23_ee421_ecg621_video – answer project questions
November 18 – lec22_ee421_ecg621.pdf and lec22_ee421_ecg621_video – answer project questions, more clocked circuits
November 13 – lec21_ee421_ecg621.pdf and lec21_ee421_ecg621_video – clocked circuits, setup and hold times, metastability
November 11 – Veterans Day (no lecture)
November 6 – lec20_ee421_ecg621.pdf and lec20_ee421_ecg621_video – delay calculations and complex CMOS logic gate design
November 4 – lec19_ee421_ecg621.pdf and lec19_ee421_ecg621_video – review some key topics and discuss course projects
October 30 – lec18_ee421_ecg621.pdf and lec18_ee421_ecg621_video – continue with the CMOS inverter, static logic gates
October 28 – lec17_ee421_ecg621.pdf and lec17_ee421_ecg621_video – Miller effect, examples, discuss inverter switching point
October 23 – lec16_ee421_ecg621.pdf and lec16_ee421_ecg621_video – pass and transmission gates, start the CMOS inverter
October 21 – lec15_ee421_ecg621.pdf and lec15_ee421_ecg621_video – start Ch. 10, models for digital design
October 16 – lec14_ee421_ecg621.pdf and lec14_ee421_ecg621_video – discuss course projects
October 14 – Midterm, open book and closed notes (practice_midterm)
October 9 – lec13_ee421_ecg621.pdf and lec13_ee421_ecg621_video – review for the midterm exam
October 7 – lec12_ee421_ecg621.pdf and lec12_ee421_ecg621_video – MOSFET in the triode and saturation region, on/off currents
October 2 – lec11_ee421_ecg621.pdf and lec11_ee421_ecg621_video – finish threshold voltage, body effect, subthreshold operation
September 30 – lec10_ee421_ecg621.pdf and lec10_ee421_ecg621_video – strong inversion, depletion, accumulation, start threshold voltage
September 25 – lec9_ee421_ecg621.pdf and lec9_ee421_ecg621_video – hi-res resistors in C5, poly-poly capacitors, using unit elements
September 23 – lec8_ee421_ecg621.pdf and lec8_ee421_ecg621_video – laying out wide MOSFETs, Cadence examples
September 18 – lec7_ee421_ecg621.pdf and lec7_ee421_ecg621_video – layout of a MOSFET, the active and poly layers, substrate/well contacts
September 16 – lec6_ee421_ecg621.pdf and lec6_ee421_ecg621_video – delay through the metal layers, crosstalk and ground bounce
September 11 – lec5_ee421_ecg621.pdf and lec5_ee421_ecg621_video – the metal layers, layout out a bond pad, capacitance, vias
September 9 – lec4_ee421_ecg621.pdf and lec4_ee421_ecg621_video – reverse recovery time of a forward biased diode
September 4 – lec3_ee421_ecg621.pdf and lec3_ee421_ecg621_video – depletion capacitance, RC delay through an n-well resistor
September 2 – Labor Day Recess
August 28 – lec2_ee421_ecg621.pdf and lec2_ee421_ecg621_video – making a design directory in Cadence for the C5 process, start Ch. 2, The Well
August 26 – lec1_ee421_ecg621.pdf and lec1_ee421_ecg621_video – course introduction, setting up Cadence